Submicron technologies, enabling the implementation of SoC's, are gaining acceptance and this represents a major step forward in design and test complexity. As a result, new tools and development flows are needed that will be able to handle the greater design and test challenges of increasingly smaller geometries. Besides digital, processor and memory cores, SoC's in addition incorporate analog, mixed signal (like data converters) and even MEMS cores. In the case of analog and mixed signal cores, determining the coverage of tests in terms of potential defects by fault simulation is still a very time-consuming process. A fault simulator remains an essential tool in accomplishing optimal test-signal generation. Functional test generation is still a manual job, but structural test generation can be automated and research is continuing in both areas. The nature of the resulting test signals is quite an issue because of the excessively expensive mixed signal Automatic Test Equipment (ATE) and possible on-chip generation.