Analysing degradation effects in charge-redistribution SAR ADCs

M.A. Khan, Hans G. Kerkhoff

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    2 Citations (Scopus)
    15 Downloads (Pure)

    Abstract

    Aging-sensitive technology nodes that are resulting in performance degradations in their electronic system implementations require aging simulations in advance for a more dependable design. Simulating time-domain aging effects in these electronic systems, especially in complex analog and mixed-signal systems like analog-to-digital converters, are time consuming and is often impossible for larger designs. The current paper investigates the degradation effects in the performance parameters of a mixed-signal system, a charge-redistribution successive approximation register (SAR) ADC, by using a system-level approach. In this approach the whole system has been divided into its sub-building blocks and the degradation effects of each individual building block have been incorporated into its system-level models. Furthermore, these system-level models have been simulated in LabVIEW in order to investigate the aging effects in static and dynamic performance parameters of a charge-redistribution SAR ADC due to the degradation in its building blocks. The sensitivity of the different static and dynamic performance parameters of the modelled ADC show that the presented technique is efficient to provide information about the aging effects to mixed-signal system designers and that they can use it to produce a more dependable design.
    Original languageUndefined
    Title of host publication26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013
    Place of PublicationLos Alamitos, CA, USA
    PublisherIEEE
    Pages65-70
    Number of pages6
    ISBN (Print)978-1-4799-1583-5
    DOIs
    Publication statusPublished - 2 Oct 2013
    Event2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013 - New York, United States
    Duration: 2 Oct 20134 Oct 2013

    Publication series

    Name
    PublisherIEEE
    ISSN (Print)1550-5774

    Conference

    Conference2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013
    Abbreviated titleDFT
    CountryUnited States
    CityNew York
    Period2/10/134/10/13

    Keywords

    • CAES-TDT: Testable Design and Test
    • EWI-23928
    • charge-redistribution SAR ADC
    • degradation analysis
    • IR-87765
    • Degradation modelling
    • Sensitivity analysis
    • METIS-300135
    • dependable design

    Cite this