Analysis and Design of a Low-Loss 1–10 GHz Capacitive Stacking N-Path Filter/Mixer

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Abstract

Abstract:
This article presents a capacitive stacking N -path filter/mixer optimized for low losses over a wide 1–10 GHz RF range, implemented in 22-nm fully depleted silicon-on-insulator (FDSOI) technology. By making the baseband (BB) capacitor larger than the RF capacitor, the former will define the bandwidth (BW). As a result, the RF capacitor can be much smaller, effectively reducing the parasitic capacitance at the RF node and limiting the loss at 10 GHz to only 1.4 dB. The implications and limitations of this capacitive scaling technique are explored, and an eigenvalue-based analysis is presented to derive a transfer function (TF) and simple design equations. Using these design equations, a prototype has been implemented that achieves 20-MHz channel BW while occupying 0.05 mm 2 of active area. The design consumes 3.1-mW/GHz dynamic power with negligible static power and obtains a noise figure (NF) of 4.7–7.0 dB over an RF range of 1–10 GHz. The in-band (IB) input-referred third-order intercept point (IIP 3 ) is over 1 dBm across the RF range and across three samples, while the out-of-band IIP 3 is 17–28 dBm.
Original languageEnglish
Pages (from-to)1-15
JournalIEEE journal of solid-state circuits
DOIs
Publication statusE-pub ahead of print/First online - 12 Jul 2024

Keywords

  • Capacitors , Radio frequency , Parasitic capacitance , Circuit analysis , Harmonic analysis , Noise measurement , Silicon-on-insulator , Loss measurement , Energy consumption , Intermodulation distortion , Impedance , Transformers , Software radio , Filters , Mixers

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