Analysis of Random Jitter in a Clock Multiplying DLL Architecture

R.C.H. van de Beek, E.A.M. Klumperink, C.S. Vaucher, Bram Nauta

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    In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.
    Original languageEnglish
    Title of host publicationProceedings SAFE, ProRISC, SeSens 2001
    Subtitle of host publicationNovember 28-30 2001, Veldhoven, the Netherlands
    Place of PublicationUtrecht
    Number of pages7
    ISBN (Print)90-73461-29-4
    Publication statusPublished - Nov 2001
    Event14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003 - Veldhoven, Netherlands
    Duration: 25 Nov 200327 Nov 2003
    Conference number: 14


    Workshop14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003
    Abbreviated titleProRISC

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