Analysis of Random Jitter in a Clock Multiplying DLL Architecture

R.C.H. van de Beek; E.A.M. Klumperink; C.S. Vaucher; Bram Nauta

Analysis of Random Jitter in a Clock Multiplying DLL Architecture

R.C.H. van de Beek, E.A.M. Klumperink, C.S. Vaucher, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic

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Abstract

In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.

Original language	English
Title of host publication	Proceedings SAFE, ProRISC, SeSens 2001
Subtitle of host publication	November 28-30 2001, Veldhoven, the Netherlands
Place of Publication	Utrecht
Publisher	STW
Pages	281-287
Number of pages	7
ISBN (Print)	90-73461-29-4
Publication status	Published - Nov 2001
Event	14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003 - Veldhoven, Netherlands Duration: 25 Nov 2003 → 27 Nov 2003 Conference number: 14

Workshop

Workshop	14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003
Abbreviated title	ProRISC
Country/Territory	Netherlands
City	Veldhoven
Period	25/11/03 → 27/11/03

Access to Document

Beek2001analysisFinal published version, 606 KB

1 Poster

Analysis of Random Jitter in a Clock Multiplying DLL Architecture
van de Beek, R. C. H., Klumperink, E. A. M., Vaucher, C. S. & Nauta, B., 29 Nov 2001. 1 p.
Research output: Contribution to conference › Poster › Other research output

Cite this

@inproceedings{a20b23189dae4352b2a0fea5147685c4,

title = "Analysis of Random Jitter in a Clock Multiplying DLL Architecture",

abstract = "In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.",

author = "{van de Beek}, R.C.H. and E.A.M. Klumperink and C.S. Vaucher and Bram Nauta",

year = "2001",

month = nov,

language = "English",

isbn = "90-73461-29-4",

pages = "281--287",

booktitle = "Proceedings SAFE, ProRISC, SeSens 2001",

publisher = "STW",

note = "14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003, ProRISC ; Conference date: 25-11-2003 Through 27-11-2003",

}

TY - GEN

T1 - Analysis of Random Jitter in a Clock Multiplying DLL Architecture

AU - van de Beek, R.C.H.

AU - Klumperink, E.A.M.

AU - Vaucher, C.S.

AU - Nauta, Bram

N1 - Conference code: 14

PY - 2001/11

Y1 - 2001/11

N2 - In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.

AB - In this paper, a thorough analysis of the jitter behavior of a Delay Locked Loop (DLL) based clock multiplying architecture is presented. The noise sources that are included in the analysis are the noise of the delay elements, the reference jitter and the noise of the Phase Frequency Detector and Charge Pump combination. It is shown that the effect of all noise sources on the output timing jitter can be minimized by minimizing the loop gain of the DLL. This means that the loop is merely used to tune the delay of the Delay Line to a nominal value of exactly one reference input period; the loop is ineffective in filtering jitter. The analysis results are verified using high-level simulations, with good agreement.

M3 - Conference contribution

SN - 90-73461-29-4

SP - 281

EP - 287

BT - Proceedings SAFE, ProRISC, SeSens 2001

PB - STW

CY - Utrecht

T2 - 14th ProRISC Workshop on Circuits, Systems and Signal Processing 2003

Y2 - 25 November 2003 through 27 November 2003

ER -