• 8 Citations

Abstract

Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.
LanguageUndefined
Title of host publication22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014
Place of PublicationUSA
PublisherIEEE Computer Society
Pages512-519
Number of pages8
ISBN (Print)978-1-4799-2728-9
DOIs
StatePublished - 2014
Event22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014 - Turin, Italy
Duration: 12 Feb 201414 Feb 2014
Conference number: 22

Publication series

Name
PublisherIEEE Computer Society
ISSN (Print)1066-6192

Conference

Conference22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014
Abbreviated titlePDP
CountryItaly
CityTurin
Period12/02/1414/02/14

Keywords

  • EWI-24562
  • CAES-EEA: Efficient Embedded Architectures
  • EC Grant Agreement nr.: FP7/2007-2013
  • EC Grant Agreement nr.: FP7/318490
  • METIS-304019
  • Dynamic voltage and frequency scaling
  • Parallel processing
  • IR-90567
  • Mathematical Programming
  • Energy minimization

Cite this

Gerards, M. E. T., Hurink, J. L., Holzenspies, P. K. F., Kuper, J., & Smit, G. J. M. (2014). Analytic clock frequency selection for global DVFS. In 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014 (pp. 512-519). USA: IEEE Computer Society. DOI: 10.1109/PDP.2014.103
Gerards, Marco Egbertus Theodorus ; Hurink, Johann L. ; Holzenspies, P.K.F. ; Kuper, Jan ; Smit, Gerardus Johannes Maria. / Analytic clock frequency selection for global DVFS. 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014. USA : IEEE Computer Society, 2014. pp. 512-519
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abstract = "Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.",
keywords = "EWI-24562, CAES-EEA: Efficient Embedded Architectures, EC Grant Agreement nr.: FP7/2007-2013, EC Grant Agreement nr.: FP7/318490, METIS-304019, Dynamic voltage and frequency scaling, Parallel processing, IR-90567, Mathematical Programming, Energy minimization",
author = "Gerards, {Marco Egbertus Theodorus} and Hurink, {Johann L.} and P.K.F. Holzenspies and Jan Kuper and Smit, {Gerardus Johannes Maria}",
note = "eemcs-eprint-24562",
year = "2014",
doi = "10.1109/PDP.2014.103",
language = "Undefined",
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publisher = "IEEE Computer Society",
pages = "512--519",
booktitle = "22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014",
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Gerards, MET, Hurink, JL, Holzenspies, PKF, Kuper, J & Smit, GJM 2014, Analytic clock frequency selection for global DVFS. in 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014. IEEE Computer Society, USA, pp. 512-519, 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014, Turin, Italy, 12/02/14. DOI: 10.1109/PDP.2014.103

Analytic clock frequency selection for global DVFS. / Gerards, Marco Egbertus Theodorus; Hurink, Johann L.; Holzenspies, P.K.F.; Kuper, Jan; Smit, Gerardus Johannes Maria.

22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014. USA : IEEE Computer Society, 2014. p. 512-519.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Analytic clock frequency selection for global DVFS

AU - Gerards,Marco Egbertus Theodorus

AU - Hurink,Johann L.

AU - Holzenspies,P.K.F.

AU - Kuper,Jan

AU - Smit,Gerardus Johannes Maria

N1 - eemcs-eprint-24562

PY - 2014

Y1 - 2014

N2 - Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.

AB - Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.

KW - EWI-24562

KW - CAES-EEA: Efficient Embedded Architectures

KW - EC Grant Agreement nr.: FP7/2007-2013

KW - EC Grant Agreement nr.: FP7/318490

KW - METIS-304019

KW - Dynamic voltage and frequency scaling

KW - Parallel processing

KW - IR-90567

KW - Mathematical Programming

KW - Energy minimization

U2 - 10.1109/PDP.2014.103

DO - 10.1109/PDP.2014.103

M3 - Conference contribution

SN - 978-1-4799-2728-9

SP - 512

EP - 519

BT - 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014

PB - IEEE Computer Society

CY - USA

ER -

Gerards MET, Hurink JL, Holzenspies PKF, Kuper J, Smit GJM. Analytic clock frequency selection for global DVFS. In 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014. USA: IEEE Computer Society. 2014. p. 512-519. Available from, DOI: 10.1109/PDP.2014.103