Analytic clock frequency selection for global DVFS

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Abstract

Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is used in modern multicore processors like the IBM Power 7, ARM Cortex A9 and NVIDIA Tegra 2. This theory oriented paper discusses energy optimal DVFS algorithms for such processors. There are no known provably optimal algorithms that minimize the energy consumption of nontrivial real-time applications on a global DVFS system. Such algorithms only exist for single core systems, or for simpler application models. While many DVFS algorithms focus on tasks, this theoretical study is conceptually different and focuses on the amount of parallelism. We provide a transformation from a multicore problem to a single core problem, by using the amount of parallelism of an application. Then existing single core algorithms can be used to find the optimal solution. Furthermore, we extend an existing single core algorithm such that it takes static power into account.
Original languageUndefined
Title of host publication22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014
Place of PublicationUSA
PublisherIEEE Computer Society
Pages512-519
Number of pages8
ISBN (Print)978-1-4799-2728-9
DOIs
Publication statusPublished - 2014
Event22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014 - Turin, Italy
Duration: 12 Feb 201414 Feb 2014
Conference number: 22

Publication series

Name
PublisherIEEE Computer Society
ISSN (Print)1066-6192

Conference

Conference22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014
Abbreviated titlePDP
CountryItaly
CityTurin
Period12/02/1414/02/14

Keywords

  • EWI-24562
  • CAES-EEA: Efficient Embedded Architectures
  • EC Grant Agreement nr.: FP7/2007-2013
  • EC Grant Agreement nr.: FP7/318490
  • METIS-304019
  • Dynamic voltage and frequency scaling
  • Parallel processing
  • IR-90567
  • Mathematical Programming
  • Energy minimization

Cite this

Gerards, M. E. T., Hurink, J. L., Holzenspies, P. K. F., Kuper, J., & Smit, G. J. M. (2014). Analytic clock frequency selection for global DVFS. In 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014 (pp. 512-519). USA: IEEE Computer Society. https://doi.org/10.1109/PDP.2014.103