Analytical approaches for performance evaluation of networks-on-chip

Abbas Eslami Kiasari, Axel Jantsch, Marco Jan Gerrit Bekooij, Alan Burns, Zhonghai Lu

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

    1 Citation (Scopus)
    163 Downloads (Pure)

    Abstract

    This tutorial reviews four popular mathematical formalisms – dataflow analysis, schedulability analysis, network calculus, and queueing theory – and how they have been applied to the analysis of Network-on-Chip (NoC) performance. We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis. The tutorial also discusses the respective strengths and weaknesses of each formalism, their suitability for a specific purpose, and the attempts that have been made to bridge these analytical approaches. Finally, we conclude the tutorial by discussing open research issues.
    Original languageUndefined
    Title of host publicationProceedings of the 2012 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2012
    Place of PublicationNew York
    PublisherAssociation for Computing Machinery
    Pages211-212
    Number of pages2
    ISBN (Print)978-1-4503-1424-4
    DOIs
    Publication statusPublished - 7 Oct 2012
    EventInternational Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2012 - Tampere, Finland
    Duration: 7 Oct 201212 Oct 2012

    Publication series

    Name
    PublisherACM

    Conference

    ConferenceInternational Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2012
    Abbreviated titleCASES
    Country/TerritoryFinland
    CityTampere
    Period7/10/1212/10/12

    Keywords

    • EWI-22539
    • METIS-293199
    • IR-83418
    • Performance analysis of networks-on-chip

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