This tutorial reviews four popular mathematical formalisms –
dataflow analysis, schedulability analysis, network calculus, and queueing theory – and how they have been applied to the analysis of Network-on-Chip (NoC) performance. We review the basic concepts and results of each formalism and provide examples of how they have been used in on-chip communication performance analysis. The tutorial also discusses the respective strengths and
weaknesses of each formalism, their suitability for a specific purpose, and the attempts that have been made to bridge these analytical approaches. Finally, we conclude the tutorial by discussing open research issues.
|Conference||International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2012|
|Period||7/10/12 → 12/10/12|
- Performance analysis of networks-on-chip