Application of laser annealing in the EU FP6 project D-DotFET

L. K. Nanver; V. Jovanović; C. Biasotto; J. Van Der Cingel; S. Milosavljević

doi:10.1109/RTP.2009.5373443

Application of laser annealing in the EU FP6 project D-DotFET

L. K. Nanver, V. Jovanović, C. Biasotto, J. Van Der Cingel, S. Milosavljević

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

Full-melt high-power excimer laser annealing is investigated as a means of activating implanted source/drain regions in a MISFET structure, which could be positioned on a SiGe dot in such a manner that strain is transferred to the channel region. Such a "DotFET" device is the focus of the EU FP6 project D-DotFET. A MISFET structure fabricated at suitably low processing temperatures, below 400 °C, is demonstrated with a metal/high-k gate-stack that is self-aligned to laser-annealed S/D regions.

Original language	English
Title of host publication	17th IEEE Conference on Advanced Thermal Processing of Semiconductors, RTP 2009
DOIs	https://doi.org/10.1109/RTP.2009.5373443
Publication status	Published - 1 Dec 2009
Externally published	Yes
Event	2009 17th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2009 - Albany, United States Duration: 29 Sept 2009 → 2 Oct 2009

Conference

Conference	2009 17th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2009
Abbreviated title	RTP 2009
Country/Territory	United States
City	Albany
Period	29/09/09 → 2/10/09

Access to Document

10.1109/RTP.2009.5373443

Cite this

@inproceedings{3c515b2142414cc686abcb5bf0db09e6,

title = "Application of laser annealing in the EU FP6 project D-DotFET",

abstract = "Full-melt high-power excimer laser annealing is investigated as a means of activating implanted source/drain regions in a MISFET structure, which could be positioned on a SiGe dot in such a manner that strain is transferred to the channel region. Such a {"}DotFET{"} device is the focus of the EU FP6 project D-DotFET. A MISFET structure fabricated at suitably low processing temperatures, below 400 °C, is demonstrated with a metal/high-k gate-stack that is self-aligned to laser-annealed S/D regions.",

author = "Nanver, {L. K.} and V. Jovanovi{\'c} and C. Biasotto and {Van Der Cingel}, J. and S. Milosavljevi{\'c}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/RTP.2009.5373443",

language = "English",

isbn = "9781424438150",

booktitle = "17th IEEE Conference on Advanced Thermal Processing of Semiconductors, RTP 2009",

note = "2009 17th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2009, RTP 2009 ; Conference date: 29-09-2009 Through 02-10-2009",

}

Nanver, LK, Jovanović, V, Biasotto, C, Van Der Cingel, J & Milosavljević, S 2009, Application of laser annealing in the EU FP6 project D-DotFET. in 17th IEEE Conference on Advanced Thermal Processing of Semiconductors, RTP 2009., 5373443, 2009 17th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2009, Albany, New York, United States, 29/09/09. https://doi.org/10.1109/RTP.2009.5373443

TY - GEN

T1 - Application of laser annealing in the EU FP6 project D-DotFET

AU - Nanver, L. K.

AU - Jovanović, V.

AU - Biasotto, C.

AU - Van Der Cingel, J.

AU - Milosavljević, S.

PY - 2009/12/1

Y1 - 2009/12/1

N2 - Full-melt high-power excimer laser annealing is investigated as a means of activating implanted source/drain regions in a MISFET structure, which could be positioned on a SiGe dot in such a manner that strain is transferred to the channel region. Such a "DotFET" device is the focus of the EU FP6 project D-DotFET. A MISFET structure fabricated at suitably low processing temperatures, below 400 °C, is demonstrated with a metal/high-k gate-stack that is self-aligned to laser-annealed S/D regions.

AB - Full-melt high-power excimer laser annealing is investigated as a means of activating implanted source/drain regions in a MISFET structure, which could be positioned on a SiGe dot in such a manner that strain is transferred to the channel region. Such a "DotFET" device is the focus of the EU FP6 project D-DotFET. A MISFET structure fabricated at suitably low processing temperatures, below 400 °C, is demonstrated with a metal/high-k gate-stack that is self-aligned to laser-annealed S/D regions.

UR - http://www.scopus.com/inward/record.url?scp=77951448601&partnerID=8YFLogxK

U2 - 10.1109/RTP.2009.5373443

DO - 10.1109/RTP.2009.5373443

M3 - Conference contribution

AN - SCOPUS:77951448601

SN - 9781424438150

BT - 17th IEEE Conference on Advanced Thermal Processing of Semiconductors, RTP 2009

T2 - 2009 17th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2009

Y2 - 29 September 2009 through 2 October 2009

ER -

Application of laser annealing in the EU FP6 project D-DotFET

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this