A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.
|Publisher||IEEE Computer Society Press|
|Conference||Second ACM/IEEE International Symposium on Networks-on-Chip, NOCS|
|Period||7/04/08 → 10/04/08|
|Other||7-10 April 2008|