Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

A. Hansson, Andreas Hansson, M.H. Wiggers, Arno Moonen, Kees Goossens, Marco Jan Gerrit Bekooij, Marco Bekooij

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    23 Citations (Scopus)
    63 Downloads (Pure)

    Abstract

    A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.
    Original languageUndefined
    Title of host publicationSecond ACM/IEEE International Symposium on Networks-on-Chip (NOCS)
    Place of PublicationLos Alamitos
    PublisherIEEE Computer Society Press
    Pages211-212
    Number of pages2
    ISBN (Print)0-7695-3098-2
    DOIs
    Publication statusPublished - Apr 2008

    Publication series

    Name
    PublisherIEEE Computer Society Press
    Number274

    Keywords

    • IR-64781
    • EWI-12793
    • METIS-250991

    Cite this

    Hansson, A., Hansson, A., Wiggers, M. H., Moonen, A., Goossens, K., Bekooij, M. J. G., & Bekooij, M. (2008). Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. In Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS) (pp. 211-212). [10.1109/NOCS.2008.4492742] Los Alamitos: IEEE Computer Society Press. https://doi.org/10.1109/NOCS.2008.4492742