Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

A. Hansson; Andreas Hansson; M.H. Wiggers; Arno Moonen; Kees Goossens; Marco Jan Gerrit Bekooij; Marco Bekooij

doi:10.1109/NOCS.2008.4492742

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

A. Hansson, Andreas Hansson, M.H. Wiggers, Arno Moonen, Kees Goossens, Marco Jan Gerrit Bekooij, Marco Bekooij

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

23 Citations (Scopus)

63 Downloads (Pure)

Abstract

A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.

Original language	Undefined
Title of host publication	Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS)
Place of Publication	Los Alamitos
Publisher	IEEE Computer Society Press
Pages	211-212
Number of pages	2
ISBN (Print)	0-7695-3098-2
DOIs	https://doi.org/10.1109/NOCS.2008.4492742
Publication status	Published - Apr 2008

Publication series

Name
Publisher	IEEE Computer Society Press
Number	274

Keywords

IR-64781
EWI-12793
METIS-250991

Access to Document

10.1109/NOCS.2008.4492742

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Cite this

Hansson, A., Hansson, A., Wiggers, M. H., Moonen, A., Goossens, K., Bekooij, M. J. G., & Bekooij, M. (2008). Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. In Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS) (pp. 211-212). [10.1109/NOCS.2008.4492742] Los Alamitos: IEEE Computer Society Press. https://doi.org/10.1109/NOCS.2008.4492742

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abstract = "A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.",

keywords = "IR-64781, EWI-12793, METIS-250991",

author = "A. Hansson and Andreas Hansson and M.H. Wiggers and Arno Moonen and Kees Goossens and Bekooij, {Marco Jan Gerrit} and Marco Bekooij",

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Hansson, A, Hansson, A, Wiggers, MH, Moonen, A, Goossens, K, Bekooij, MJG & Bekooij, M 2008, Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. in Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS)., 10.1109/NOCS.2008.4492742, IEEE Computer Society Press, Los Alamitos, pp. 211-212. https://doi.org/10.1109/NOCS.2008.4492742

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. / Hansson, A.; Hansson, Andreas; Wiggers, M.H.; Moonen, Arno; Goossens, Kees; Bekooij, Marco Jan Gerrit; Bekooij, Marco.

Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS). Los Alamitos : IEEE Computer Society Press, 2008. p. 211-212 10.1109/NOCS.2008.4492742.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

AU - Hansson, A.

AU - Hansson, Andreas

AU - Wiggers, M.H.

AU - Moonen, Arno

AU - Goossens, Kees

AU - Bekooij, Marco Jan Gerrit

AU - Bekooij, Marco

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N2 - A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.

AB - A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation.

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Hansson A, Hansson A, Wiggers MH, Moonen A, Goossens K, Bekooij MJG et al. Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. In Second ACM/IEEE International Symposium on Networks-on-Chip (NOCS). Los Alamitos: IEEE Computer Society Press. 2008. p. 211-212. 10.1109/NOCS.2008.4492742 https://doi.org/10.1109/NOCS.2008.4492742