Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems

Hans G. Kerkhoff, Ghazanfar Ali, J. Wan, Ahmed Mohammed Youssef Ibrahim, Jerrin Pathrose Vareed

    Research output: Contribution to conferencePaper

    2 Citations (Scopus)

    Abstract

    In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate counteractions if required, we have accomplished this goal in the past via IJTAG compatible embedded instruments and appropriate embedded software. This paper extends this approach to the analog / mixed-signal frontends of these systems, thereby creating a new uniform approach in design & test methodology, as well as a streamlined fault management. An IJTAG-compatible voltage monitor is introduced, for measuring aging-generated offset in OpAmps and SAR ADCs, as well as a delay-monitoring embedded instrument for detecting timing issues in ADCs. In addition, two-stage counter measures, like digitized recalibration and subsequent replacement, are presented to increase the lifetime by factors of the analog front-end of Cyber-Physical Systems-on-Chips.
    Original languageEnglish
    Pages1-6
    Number of pages6
    DOIs
    Publication statusPublished - 14 Dec 2017
    Event25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017 - Abu Dhabi, United Arab Emirates
    Duration: 23 Oct 201725 Oct 2017
    Conference number: 25

    Conference

    Conference25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017
    Abbreviated titleVLSI-SoC 2017
    CountryUnited Arab Emirates
    CityAbu Dhabi
    Period23/10/1725/10/17

    Fingerprint

    Aging of materials
    Embedded software
    Monitoring
    Operational amplifiers
    Large scale systems
    Railroad cars
    Health
    Electric potential
    Cyber Physical System
    System-on-chip

    Cite this

    Kerkhoff, H. G., Ali, G., Wan, J., Ibrahim, A. M. Y., & Pathrose Vareed, J. (2017). Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems. 1-6. Paper presented at 25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017, Abu Dhabi, United Arab Emirates. https://doi.org/10.1109/VLSI-SoC.2017.8203464
    Kerkhoff, Hans G. ; Ali, Ghazanfar ; Wan, J. ; Ibrahim, Ahmed Mohammed Youssef ; Pathrose Vareed, Jerrin . / Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems. Paper presented at 25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017, Abu Dhabi, United Arab Emirates.6 p.
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    title = "Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems",
    abstract = "In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate counteractions if required, we have accomplished this goal in the past via IJTAG compatible embedded instruments and appropriate embedded software. This paper extends this approach to the analog / mixed-signal frontends of these systems, thereby creating a new uniform approach in design & test methodology, as well as a streamlined fault management. An IJTAG-compatible voltage monitor is introduced, for measuring aging-generated offset in OpAmps and SAR ADCs, as well as a delay-monitoring embedded instrument for detecting timing issues in ADCs. In addition, two-stage counter measures, like digitized recalibration and subsequent replacement, are presented to increase the lifetime by factors of the analog front-end of Cyber-Physical Systems-on-Chips.",
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    Kerkhoff, HG, Ali, G, Wan, J, Ibrahim, AMY & Pathrose Vareed, J 2017, 'Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems' Paper presented at 25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017, Abu Dhabi, United Arab Emirates, 23/10/17 - 25/10/17, pp. 1-6. https://doi.org/10.1109/VLSI-SoC.2017.8203464

    Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems. / Kerkhoff, Hans G.; Ali, Ghazanfar ; Wan, J.; Ibrahim, Ahmed Mohammed Youssef; Pathrose Vareed, Jerrin .

    2017. 1-6 Paper presented at 25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017, Abu Dhabi, United Arab Emirates.

    Research output: Contribution to conferencePaper

    TY - CONF

    T1 - Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems

    AU - Kerkhoff, Hans G.

    AU - Ali, Ghazanfar

    AU - Wan, J.

    AU - Ibrahim, Ahmed Mohammed Youssef

    AU - Pathrose Vareed, Jerrin

    PY - 2017/12/14

    Y1 - 2017/12/14

    N2 - In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate counteractions if required, we have accomplished this goal in the past via IJTAG compatible embedded instruments and appropriate embedded software. This paper extends this approach to the analog / mixed-signal frontends of these systems, thereby creating a new uniform approach in design & test methodology, as well as a streamlined fault management. An IJTAG-compatible voltage monitor is introduced, for measuring aging-generated offset in OpAmps and SAR ADCs, as well as a delay-monitoring embedded instrument for detecting timing issues in ADCs. In addition, two-stage counter measures, like digitized recalibration and subsequent replacement, are presented to increase the lifetime by factors of the analog front-end of Cyber-Physical Systems-on-Chips.

    AB - In safety-critical cyber-physical systems, analog front-ends combined with many-processors are being increasingly employed. An example is an imminent collision detection chip for cars. Such a complex system requires zero downtime and a very high dependability despite aging issues under harsh environmental conditions. By on-line monitoring the health status of the processor cores and taking appropriate counteractions if required, we have accomplished this goal in the past via IJTAG compatible embedded instruments and appropriate embedded software. This paper extends this approach to the analog / mixed-signal frontends of these systems, thereby creating a new uniform approach in design & test methodology, as well as a streamlined fault management. An IJTAG-compatible voltage monitor is introduced, for measuring aging-generated offset in OpAmps and SAR ADCs, as well as a delay-monitoring embedded instrument for detecting timing issues in ADCs. In addition, two-stage counter measures, like digitized recalibration and subsequent replacement, are presented to increase the lifetime by factors of the analog front-end of Cyber-Physical Systems-on-Chips.

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    DO - 10.1109/VLSI-SoC.2017.8203464

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    Kerkhoff HG, Ali G, Wan J, Ibrahim AMY, Pathrose Vareed J. Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems. 2017. Paper presented at 25th IFIP/IEEE International Conference on Very Large Scale Intergration 2017, Abu Dhabi, United Arab Emirates. https://doi.org/10.1109/VLSI-SoC.2017.8203464