Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

A fast wafer level reliability structure and evaluation method has been developed for stress induced leakage current (SILC) in non-volatile memory processes. The structure is based on parallel floating gate cell arrays. The evaluation method is straightforward, and not time-consuming. The measurement consists of bi-directional FN tunneling stress (to degrade the tunnel oxide and to develop the SILC) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell Vt in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded Flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.