Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

Maarten H. Wiggers, Nikolay Kavaldjiev, Gerard J.M. Smit, Pierre G. Jansen

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    Abstract

    We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
    Original languageEnglish
    Title of host publicationCommunicating Process Architectures 2005 (WoTUG-28)
    EditorsJan F. Broenink, Herman W. Roebbers, Johan P.E Sunter, Peter H. Welch, David C. Wood
    Place of PublicationAmsterdam
    PublisherIOS Press
    Pages219-233
    Number of pages15
    ISBN (Print)1-58603-561-4
    Publication statusPublished - Sep 2005
    EventCommunicating Process Architectures, CPA 2005: 28th WoTUG Conference on Concurrent and Parallel Programming - Eindhoven, Netherlands
    Duration: 18 Sep 200521 Sep 2005
    Conference number: 28

    Publication series

    NameConcurrent Systems Engineering Series
    PublisherIOS Press
    Volume63
    ISSN (Print)1383-7575
    ISSN (Electronic)1879-8039

    Conference

    ConferenceCommunicating Process Architectures, CPA 2005
    Abbreviated titleCPA
    CountryNetherlands
    CityEindhoven
    Period18/09/0521/09/05

    Keywords

    • CAES-EEA: Efficient Embedded Architectures

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