Abstract
We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
Original language | English |
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Title of host publication | Communicating Process Architectures 2005 (WoTUG-28) |
Editors | Jan F. Broenink, Herman W. Roebbers, Johan P.E Sunter, Peter H. Welch, David C. Wood |
Place of Publication | Amsterdam |
Publisher | IOS Press |
Pages | 219-233 |
Number of pages | 15 |
ISBN (Print) | 1-58603-561-4 |
Publication status | Published - Sep 2005 |
Event | Communicating Process Architectures, CPA 2005: 28th WoTUG Conference on Concurrent and Parallel Programming - Eindhoven, Netherlands Duration: 18 Sep 2005 → 21 Sep 2005 Conference number: 28 |
Publication series
Name | Concurrent Systems Engineering Series |
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Publisher | IOS Press |
Volume | 63 |
ISSN (Print) | 1383-7575 |
ISSN (Electronic) | 1879-8039 |
Conference
Conference | Communicating Process Architectures, CPA 2005 |
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Abbreviated title | CPA |
Country/Territory | Netherlands |
City | Eindhoven |
Period | 18/09/05 → 21/09/05 |
Keywords
- CAES-EEA: Efficient Embedded Architectures