Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

Maarten H. Wiggers; Nikolay Kavaldjiev; Gerard J.M. Smit; Pierre G. Jansen

Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

Maarten H. Wiggers, Nikolay Kavaldjiev, Gerard J.M. Smit, Pierre G. Jansen

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

20 Downloads (Pure)

Abstract

We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.

Original language	English
Title of host publication	Communicating Process Architectures 2005 (WoTUG-28)
Editors	Jan F. Broenink, Herman W. Roebbers, Johan P.E Sunter, Peter H. Welch, David C. Wood
Place of Publication	Amsterdam
Publisher	IOS Press
Pages	219-233
Number of pages	15
ISBN (Print)	1-58603-561-4
Publication status	Published - Sep 2005
Event	Communicating Process Architectures, CPA 2005: 28th WoTUG Conference on Concurrent and Parallel Programming - Eindhoven, Netherlands Duration: 18 Sep 2005 → 21 Sep 2005 Conference number: 28

Publication series

Name	Concurrent Systems Engineering Series
Publisher	IOS Press
Volume	63
ISSN (Print)	1383-7575
ISSN (Electronic)	1879-8039

Conference

Conference	Communicating Process Architectures, CPA 2005
Abbreviated title	CPA
Country	Netherlands
City	Eindhoven
Period	18/09/05 → 21/09/05

Keywords

CAES-EEA: Efficient Embedded Architectures

Access to Document

Wiggers2005architecture
open
Accepted author version, 178 KB

http://ebooks.iospress.nl/volumearticle/1549

Fingerprint Dive into the research topics of 'Architecture Design Space Exploration for Streaming Applications Through Timing Analysis'. Together they form a unique fingerprint.

Cite this

Wiggers, M. H., Kavaldjiev, N., Smit, G. J. M., & Jansen, P. G. (2005). Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. In J. F. Broenink, H. W. Roebbers, J. P. E. Sunter, P. H. Welch, & D. C. Wood (Eds.), Communicating Process Architectures 2005 (WoTUG-28) (pp. 219-233). (Concurrent Systems Engineering Series; Vol. 63). IOS Press. http://ebooks.iospress.nl/volumearticle/1549

Wiggers, Maarten H. ; Kavaldjiev, Nikolay ; Smit, Gerard J.M. ; Jansen, Pierre G. / Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. Communicating Process Architectures 2005 (WoTUG-28). editor / Jan F. Broenink ; Herman W. Roebbers ; Johan P.E Sunter ; Peter H. Welch ; David C. Wood. Amsterdam : IOS Press, 2005. pp. 219-233 (Concurrent Systems Engineering Series).

@inproceedings{44d87bad0dd14826886ad4b509cc1e88,

title = "Architecture Design Space Exploration for Streaming Applications Through Timing Analysis",

abstract = "We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.",

keywords = "CAES-EEA: Efficient Embedded Architectures",

author = "Wiggers, {Maarten H.} and Nikolay Kavaldjiev and Smit, {Gerard J.M.} and Jansen, {Pierre G.}",

year = "2005",

month = sep,

language = "English",

isbn = "1-58603-561-4",

series = "Concurrent Systems Engineering Series",

publisher = "IOS Press",

pages = "219--233",

editor = "Broenink, {Jan F.} and Roebbers, {Herman W.} and Sunter, {Johan P.E} and Welch, {Peter H.} and Wood, {David C.}",

booktitle = "Communicating Process Architectures 2005 (WoTUG-28)",

address = "Netherlands",

note = "Communicating Process Architectures, CPA 2005 : 28th WoTUG Conference on Concurrent and Parallel Programming, CPA ; Conference date: 18-09-2005 Through 21-09-2005",

}

Wiggers, MH, Kavaldjiev, N, Smit, GJM & Jansen, PG 2005, Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. in JF Broenink, HW Roebbers, JPE Sunter, PH Welch & DC Wood (eds), Communicating Process Architectures 2005 (WoTUG-28). Concurrent Systems Engineering Series, vol. 63, IOS Press, Amsterdam, pp. 219-233, Communicating Process Architectures, CPA 2005, Eindhoven, Netherlands, 18/09/05. <http://ebooks.iospress.nl/volumearticle/1549>

Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. / Wiggers, Maarten H.; Kavaldjiev, Nikolay; Smit, Gerard J.M.; Jansen, Pierre G.

Communicating Process Architectures 2005 (WoTUG-28). ed. / Jan F. Broenink; Herman W. Roebbers; Johan P.E Sunter; Peter H. Welch; David C. Wood. Amsterdam : IOS Press, 2005. p. 219-233 (Concurrent Systems Engineering Series; Vol. 63).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

AU - Wiggers, Maarten H.

AU - Kavaldjiev, Nikolay

AU - Smit, Gerard J.M.

AU - Jansen, Pierre G.

N1 - Conference code: 28

PY - 2005/9

Y1 - 2005/9

N2 - We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.

AB - We compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN\2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the applications throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.

KW - CAES-EEA: Efficient Embedded Architectures

M3 - Conference contribution

SN - 1-58603-561-4

T3 - Concurrent Systems Engineering Series

SP - 219

EP - 233

BT - Communicating Process Architectures 2005 (WoTUG-28)

A2 - Broenink, Jan F.

A2 - Roebbers, Herman W.

A2 - Sunter, Johan P.E

A2 - Welch, Peter H.

A2 - Wood, David C.

PB - IOS Press

CY - Amsterdam

T2 - Communicating Process Architectures, CPA 2005

Y2 - 18 September 2005 through 21 September 2005

ER -