Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

Maarten H. Wiggers, Nikolay Kavaldjiev, Gerard J.M. Smit, Pierre G. Jansen

    Research output: Book/ReportReportProfessional

    1 Citation (Scopus)
    22 Downloads (Pure)

    Abstract

    In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application's throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
    Original languageEnglish
    Place of PublicationEnschede
    PublisherUniversity of Twente
    Number of pages15
    Publication statusPublished - Aug 2005

    Publication series

    NameCTIT Technical Report Series
    PublisherUniversity of Twente, Centre for Telematica and Information Technology (CTIT)
    No.TR-CTIT-05-36
    ISSN (Print)1381-3625

    Keywords

    • CAES-EEA: Efficient Embedded Architectures

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  • Cite this

    Wiggers, M. H., Kavaldjiev, N., Smit, G. J. M., & Jansen, P. G. (2005). Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. (CTIT Technical Report Series; No. TR-CTIT-05-36). Enschede: University of Twente.