Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

M.H. Wiggers, N.K. Kavaldjiev, Gerardus Johannes Maria Smit, P.G. Jansen

Research output: Book/ReportReportProfessional

1 Citation (Scopus)
17 Downloads (Pure)

Abstract

In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application's throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
Original languageUndefined
Place of PublicationEnschede
PublisherDistributed and Embedded Security (DIES)
Number of pages15
Publication statusPublished - Aug 2005

Publication series

NameCTIT Technical Report Series
PublisherUniversity of Twente, Centre for Telematica and Information Technology (CTIT)
No.TR-CTIT-05-36
ISSN (Print)1381-3625

Keywords

  • CAES-EEA: Efficient Embedded Architectures
  • IR-57032
  • METIS-248105
  • EWI-5733

Cite this

Wiggers, M. H., Kavaldjiev, N. K., Smit, G. J. M., & Jansen, P. G. (2005). Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. (CTIT Technical Report Series; No. TR-CTIT-05-36). Enschede: Distributed and Embedded Security (DIES).
Wiggers, M.H. ; Kavaldjiev, N.K. ; Smit, Gerardus Johannes Maria ; Jansen, P.G. / Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. Enschede : Distributed and Embedded Security (DIES), 2005. 15 p. (CTIT Technical Report Series; TR-CTIT-05-36).
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Wiggers, MH, Kavaldjiev, NK, Smit, GJM & Jansen, PG 2005, Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. CTIT Technical Report Series, no. TR-CTIT-05-36, Distributed and Embedded Security (DIES), Enschede.

Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. / Wiggers, M.H.; Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria; Jansen, P.G.

Enschede : Distributed and Embedded Security (DIES), 2005. 15 p. (CTIT Technical Report Series; No. TR-CTIT-05-36).

Research output: Book/ReportReportProfessional

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T1 - Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

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Y1 - 2005/8

N2 - In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application's throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.

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Wiggers MH, Kavaldjiev NK, Smit GJM, Jansen PG. Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. Enschede: Distributed and Embedded Security (DIES), 2005. 15 p. (CTIT Technical Report Series; TR-CTIT-05-36).