In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application's throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations.
|Place of Publication||Enschede|
|Publisher||University of Twente|
|Number of pages||15|
|Publication status||Published - Aug 2005|
|Name||CTIT Technical Report Series|
|Publisher||University of Twente, Centre for Telematica and Information Technology (CTIT)|
- CAES-EEA: Efficient Embedded Architectures
Wiggers, M. H., Kavaldjiev, N., Smit, G. J. M., & Jansen, P. G. (2005). Architecture Design Space Exploration for Streaming Applications Through Timing Analysis. (CTIT Technical Report Series; No. TR-CTIT-05-36). Enschede: University of Twente.