Architecture of Low Cost, Large Scale Neural Networks

Stef Joosten

    Research output: Chapter in Book/Report/Conference proceedingChapterAcademic

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    Abstract

    This poster describes ideas about implementing a neurocomputer in hardware. The architecture can cope with large amounts of neurons (in the range of 103 -106), with a large number of inputs per neuron (about 103–104). The architecture exploits wafer scale integration and integrated optics
    Original languageEnglish
    Title of host publicationICANN ’93
    Subtitle of host publicationProceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993
    EditorsStan Gielen, Bert Kappen
    Place of PublicationLondon
    PublisherSpringer
    Pages1083-1083
    Number of pages1
    ISBN (Electronic)978-1-4471-2063-6
    ISBN (Print)978-3-540-19839-0
    DOIs
    Publication statusPublished - 1993
    EventInternational Conference on Artificial Neural Networks, ICANN 1993 - Amsterdam, Netherlands
    Duration: 13 Sep 199316 Sep 1993

    Conference

    ConferenceInternational Conference on Artificial Neural Networks, ICANN 1993
    Abbreviated titleICANN
    CountryNetherlands
    CityAmsterdam
    Period13/09/9316/09/93

    Keywords

    • Neural networks
    • Neural computer
    • Wafer scale integration
    • Optical computing
    • Integrated sensors and actuators

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  • Cite this

    Joosten, S. (1993). Architecture of Low Cost, Large Scale Neural Networks. In S. Gielen, & B. Kappen (Eds.), ICANN ’93: Proceedings of the International Conference on Artificial Neural Networks Amsterdam, The Netherlands 13–16 September 1993 (pp. 1083-1083). London: Springer. https://doi.org/10.1007/978-1-4471-2063-6_320