Architectures for block Toeplitz systems

Ilias Bouras, George-Othon Glentis, Nicholas Kalouptsidis

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    In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given.
    Original languageEnglish
    Pages (from-to)167-190
    Number of pages24
    JournalSignal processing
    Issue number3
    Publication statusPublished - 1996


    • Multichannel Schur algorithms
    • Toeplitz matrices
    • Parallel processing
    • VLSI implementation


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