Architectures for block Toeplitz systems

Ilias Bouras; George-Othon Glentis; Nicholas Kalouptsidis

doi:10.1016/0165-1684(96)00041-2

Architectures for block Toeplitz systems

Ilias Bouras
, George-Othon Glentis
, Nicholas Kalouptsidis

Research output: Contribution to journal › Article › Academic › peer-review

1 Citation (Scopus)

221 Downloads (Pure)

Abstract

In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given.

Original language	English
Pages (from-to)	167-190
Number of pages	24
Journal	Signal processing
Volume	51
Issue number	3
DOIs	https://doi.org/10.1016/0165-1684(96)00041-2
Publication status	Published - 1996

Keywords

Multichannel Schur algorithms
Toeplitz matrices
Parallel processing
VLSI implementation

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Cite this

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title = "Architectures for block Toeplitz systems",

abstract = "In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given.",

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year = "1996",

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AU - Bouras, Ilias

AU - Glentis, George-Othon

AU - Kalouptsidis, Nicholas

PY - 1996

Y1 - 1996

N2 - In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given.

AB - In this paper efficient VLSI architectures of highly concurrent algorithms for the solution of block linear systems with Toeplitz or near-to-Toeplitz entries are presented. The main features of the proposed scheme are the use of scalar only operations, multiplications/divisions and additions, and the local communication which enables the development of wavefront array architecture. Both the mean squared error and the total squared error formulations are described and a variety of implementations are given.

KW - Multichannel Schur algorithms

KW - Toeplitz matrices

KW - Parallel processing

KW - VLSI implementation

U2 - 10.1016/0165-1684(96)00041-2

DO - 10.1016/0165-1684(96)00041-2

M3 - Article

SN - 0165-1684

VL - 51

SP - 167

EP - 190

JO - Signal processing

JF - Signal processing

IS - 3

ER -

Architectures for block Toeplitz systems

Abstract

Keywords

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