Attenuator

Hiraoka Tokumasa; Bram Nauta

Attenuator

Hiraoka Tokumasa (Inventor), Bram Nauta (Inventor)

Research output: Patent

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Abstract

PROBLEM TO BE SOLVED: To provide an attenuator that has higher linearity and a satisfactory frequency characteristic.

SOLUTION: Between an input terminal IN and an output terminal OUT, a combined resistance group 14 comprises a resistance group 11 including a resistance R11 and a MOS transistor M11 connected in series, and a parallel resistance R14 connected in parallel with the resistance group 11. Between the input terminal IN and a reference GND potential, a resistance group 12 includes a resistance R12 and a MOS transistor M12 connected in series, and between the output terminal OUT and the reference GND potential, a resistance group 13 includes a resistance R13 and a MOS transistor M13 connected in series. In accordance with a desired attenuation, the parallel resistance R14 is arranged such that an on resistance value of the relevant MOS transistor accounts for a smaller percentage of a combined resistance on a signal line or on a short circuit line, and then the MOS transistors are controlled such that a distortion component on the signal line and a distortion component on the short circuit line cancel each other.

Original language	English
Patent number	JP2014241554 (A)
Priority date	10/07/13
Publication status	Published - 25 Dec 2014

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JP2014241554AFinal published version, 102 KB

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Attenuator
Tokumasa, H. (Inventor) & Nauta, B. (Inventor), 25 Dec 2014, Patent No. JP2014241555A, Priority date 10 Jul 2013
Research output: Patent

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@misc{4f642e77bc4b411d89ec03c746162c51,

title = "Attenuator",

abstract = "PROBLEM TO BE SOLVED: To provide an attenuator that has higher linearity and a satisfactory frequency characteristic.SOLUTION: Between an input terminal IN and an output terminal OUT, a combined resistance group 14 comprises a resistance group 11 including a resistance R11 and a MOS transistor M11 connected in series, and a parallel resistance R14 connected in parallel with the resistance group 11. Between the input terminal IN and a reference GND potential, a resistance group 12 includes a resistance R12 and a MOS transistor M12 connected in series, and between the output terminal OUT and the reference GND potential, a resistance group 13 includes a resistance R13 and a MOS transistor M13 connected in series. In accordance with a desired attenuation, the parallel resistance R14 is arranged such that an on resistance value of the relevant MOS transistor accounts for a smaller percentage of a combined resistance on a signal line or on a short circuit line, and then the MOS transistors are controlled such that a distortion component on the signal line and a distortion component on the short circuit line cancel each other.",

author = "Hiraoka Tokumasa and Bram Nauta",

year = "2014",

month = dec,

day = "25",

language = "English",

type = "Patent",

note = "JP2014241554 (A)",

}

TY - PAT

T1 - Attenuator

AU - Tokumasa, Hiraoka

AU - Nauta, Bram

PY - 2014/12/25

Y1 - 2014/12/25

N2 - PROBLEM TO BE SOLVED: To provide an attenuator that has higher linearity and a satisfactory frequency characteristic.SOLUTION: Between an input terminal IN and an output terminal OUT, a combined resistance group 14 comprises a resistance group 11 including a resistance R11 and a MOS transistor M11 connected in series, and a parallel resistance R14 connected in parallel with the resistance group 11. Between the input terminal IN and a reference GND potential, a resistance group 12 includes a resistance R12 and a MOS transistor M12 connected in series, and between the output terminal OUT and the reference GND potential, a resistance group 13 includes a resistance R13 and a MOS transistor M13 connected in series. In accordance with a desired attenuation, the parallel resistance R14 is arranged such that an on resistance value of the relevant MOS transistor accounts for a smaller percentage of a combined resistance on a signal line or on a short circuit line, and then the MOS transistors are controlled such that a distortion component on the signal line and a distortion component on the short circuit line cancel each other.

AB - PROBLEM TO BE SOLVED: To provide an attenuator that has higher linearity and a satisfactory frequency characteristic.SOLUTION: Between an input terminal IN and an output terminal OUT, a combined resistance group 14 comprises a resistance group 11 including a resistance R11 and a MOS transistor M11 connected in series, and a parallel resistance R14 connected in parallel with the resistance group 11. Between the input terminal IN and a reference GND potential, a resistance group 12 includes a resistance R12 and a MOS transistor M12 connected in series, and between the output terminal OUT and the reference GND potential, a resistance group 13 includes a resistance R13 and a MOS transistor M13 connected in series. In accordance with a desired attenuation, the parallel resistance R14 is arranged such that an on resistance value of the relevant MOS transistor accounts for a smaller percentage of a combined resistance on a signal line or on a short circuit line, and then the MOS transistors are controlled such that a distortion component on the signal line and a distortion component on the short circuit line cancel each other.

M3 - Patent

M1 - JP2014241554 (A)

ER -

Attenuator

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Attenuator

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