Balanced comparator fabricated in ramp edge technology

A.H. Sonnenberg; G.J. Gerritsma; Horst Rogalla

doi:10.1016/S0921-4534(99)00380-9

Balanced comparator fabricated in ramp edge technology

A.H. Sonnenberg, G.J. Gerritsma, Horst Rogalla

Faculty of Science and Technology

Research output: Contribution to journal › Article › Academic › peer-review

5 Citations (Scopus)

Abstract

One of the basic elements of RSFQ circuits is the balanced comparator. We have fabricated and tested a balanced comparator in a three HTS layer technology. The junctions and inductances are located on a buried ground plane in order to reduce the inductance values. We have chosen for a buried ground plane in order to avoid heating the ramp edge junction to deposition temperatures. Correct operation of the balanced comparator has been verified by dc measurements of the switching properties. The gray zone of switching has been measured as a function of temperature and operation frequency.

Original language	Undefined
Pages (from-to)	12-15
Number of pages	4
Journal	Physica C
Volume	326-32
Issue number	326-327
DOIs	https://doi.org/10.1016/S0921-4534(99)00380-9
Publication status	Published - 1999

Keywords

Ramp edge junction
IR-74195
METIS-128835
Buried ground plane
Gray zone
Balanced comparator

Access to Document

10.1016/S0921-4534(99)00380-9

Cite this

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title = "Balanced comparator fabricated in ramp edge technology",

abstract = "One of the basic elements of RSFQ circuits is the balanced comparator. We have fabricated and tested a balanced comparator in a three HTS layer technology. The junctions and inductances are located on a buried ground plane in order to reduce the inductance values. We have chosen for a buried ground plane in order to avoid heating the ramp edge junction to deposition temperatures. Correct operation of the balanced comparator has been verified by dc measurements of the switching properties. The gray zone of switching has been measured as a function of temperature and operation frequency.",

keywords = "Ramp edge junction, IR-74195, METIS-128835, Buried ground plane, Gray zone, Balanced comparator",

author = "A.H. Sonnenberg and G.J. Gerritsma and Horst Rogalla",

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TY - JOUR

T1 - Balanced comparator fabricated in ramp edge technology

AU - Sonnenberg, A.H.

AU - Gerritsma, G.J.

AU - Rogalla, Horst

PY - 1999

Y1 - 1999

N2 - One of the basic elements of RSFQ circuits is the balanced comparator. We have fabricated and tested a balanced comparator in a three HTS layer technology. The junctions and inductances are located on a buried ground plane in order to reduce the inductance values. We have chosen for a buried ground plane in order to avoid heating the ramp edge junction to deposition temperatures. Correct operation of the balanced comparator has been verified by dc measurements of the switching properties. The gray zone of switching has been measured as a function of temperature and operation frequency.

AB - One of the basic elements of RSFQ circuits is the balanced comparator. We have fabricated and tested a balanced comparator in a three HTS layer technology. The junctions and inductances are located on a buried ground plane in order to reduce the inductance values. We have chosen for a buried ground plane in order to avoid heating the ramp edge junction to deposition temperatures. Correct operation of the balanced comparator has been verified by dc measurements of the switching properties. The gray zone of switching has been measured as a function of temperature and operation frequency.

KW - Ramp edge junction

KW - IR-74195

KW - METIS-128835

KW - Buried ground plane

KW - Gray zone

KW - Balanced comparator

U2 - 10.1016/S0921-4534(99)00380-9

DO - 10.1016/S0921-4534(99)00380-9

M3 - Article

VL - 326-32

SP - 12

EP - 15

JO - Physica C

JF - Physica C

SN - 0921-4534

IS - 326-327

ER -