BIGFET Logic

L. Spaanenburg; R.C.C. Luchtmeyer; O.W. Memelink

BIGFET Logic

L. Spaanenburg
, R.C.C. Luchtmeyer
, O.W. Memelink

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

In BIGFET logic a bipolar device is introduced in series with the driver MOS transistor using an adapted MOS process technology. The input- and output requirements of the driver component are then split over these devices: a minimum size MOS transistor giving a minimum input time constant and a bipolar transistor converting the small MOS current to the required output current. The combination results in the same driver resistance as in the original gate at an improved speed and area consumption. Additional benefits are due to novel circuit structures with a smaller gate/function ratio.

Original language	English
Title of host publication	Fifth European Solid State Circuits Conference - ESSCIRC 79
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	155-157
Number of pages	3
Edition	178
ISBN (Print)	0-85296-208-8
Publication status	Published - 1979
Event	5th European Solid-State Circuits Conference, ESSCIRC 1979 - Southampton, United Kingdom Duration: 18 Sept 1979 → 21 Sept 1979 Conference number: 5

Publication series

Name	IEE Conference Publication
Publisher	IEEE
Volume	178
ISSN (Print)	0537-9989

Conference

Conference	5th European Solid-State Circuits Conference, ESSCIRC 1979
Abbreviated title	ESSCIRC
Country/Territory	United Kingdom
City	Southampton
Period	18/09/79 → 21/09/79

Cite this

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title = "BIGFET Logic",

abstract = "In BIGFET logic a bipolar device is introduced in series with the driver MOS transistor using an adapted MOS process technology. The input- and output requirements of the driver component are then split over these devices: a minimum size MOS transistor giving a minimum input time constant and a bipolar transistor converting the small MOS current to the required output current. The combination results in the same driver resistance as in the original gate at an improved speed and area consumption. Additional benefits are due to novel circuit structures with a smaller gate/function ratio.",

author = "L. Spaanenburg and R.C.C. Luchtmeyer and O.W. Memelink",

year = "1979",

language = "English",

isbn = "0-85296-208-8",

series = "IEE Conference Publication",

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pages = "155--157",

booktitle = "Fifth European Solid State Circuits Conference - ESSCIRC 79",

address = "United States",

edition = "178",

note = "5th European Solid-State Circuits Conference, ESSCIRC 1979, ESSCIRC ; Conference date: 18-09-1979 Through 21-09-1979",

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T1 - BIGFET Logic

AU - Spaanenburg, L.

AU - Luchtmeyer, R.C.C.

AU - Memelink, O.W.

N1 - Conference code: 5

PY - 1979

Y1 - 1979

N2 - In BIGFET logic a bipolar device is introduced in series with the driver MOS transistor using an adapted MOS process technology. The input- and output requirements of the driver component are then split over these devices: a minimum size MOS transistor giving a minimum input time constant and a bipolar transistor converting the small MOS current to the required output current. The combination results in the same driver resistance as in the original gate at an improved speed and area consumption. Additional benefits are due to novel circuit structures with a smaller gate/function ratio.

AB - In BIGFET logic a bipolar device is introduced in series with the driver MOS transistor using an adapted MOS process technology. The input- and output requirements of the driver component are then split over these devices: a minimum size MOS transistor giving a minimum input time constant and a bipolar transistor converting the small MOS current to the required output current. The combination results in the same driver resistance as in the original gate at an improved speed and area consumption. Additional benefits are due to novel circuit structures with a smaller gate/function ratio.

UR - https://www.scopus.com/pages/publications/0018698143

M3 - Conference contribution

AN - SCOPUS:0018698143

SN - 0-85296-208-8

T3 - IEE Conference Publication

SP - 155

EP - 157

BT - Fifth European Solid State Circuits Conference - ESSCIRC 79

PB - IEEE

CY - Piscataway, NJ

T2 - 5th European Solid-State Circuits Conference, ESSCIRC 1979

Y2 - 18 September 1979 through 21 September 1979

ER -

BIGFET Logic

Abstract

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