Bit flip injection in processor-based architectures: A case study

G.C. Cardarilli; F. Kaddour; A. Leandri; M. Ottavi; S. Pontarelli; R. Velazco

doi:10.1109/OLT.2002.1030194

Bit flip injection in processor-based architectures: A case study

G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

31 Citations (Scopus)

Abstract

This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line "injection" and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral level processor description; being based on the so-called "saboteurs" method. Results obtained for benchmark programs executed by a widely used commercial 8-bit microprocessor, allow to validate both approaches which provide inputs for an original error rate prediction methodology. The comparison of predictions to measured error rates issued from radiation ground testing validates the proposed error rate prediction approach.

Original language	English
Title of host publication	Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	11
ISBN (Print)	0-7695-1641-6
DOIs	https://doi.org/10.1109/OLT.2002.1030194
Publication status	Published - 2002
Externally published	Yes

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10.1109/OLT.2002.1030194

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title = "Bit flip injection in processor-based architectures: A case study",

abstract = "This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line {"}injection{"} and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral level processor description; being based on the so-called {"}saboteurs{"} method. Results obtained for benchmark programs executed by a widely used commercial 8-bit microprocessor, allow to validate both approaches which provide inputs for an original error rate prediction methodology. The comparison of predictions to measured error rates issued from radiation ground testing validates the proposed error rate prediction approach.",

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T2 - A case study

AU - Cardarilli, G.C.

AU - Kaddour, F.

AU - Leandri, A.

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AU - Pontarelli, S.

AU - Velazco, R.

PY - 2002

Y1 - 2002

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AB - This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line "injection" and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral level processor description; being based on the so-called "saboteurs" method. Results obtained for benchmark programs executed by a widely used commercial 8-bit microprocessor, allow to validate both approaches which provide inputs for an original error rate prediction methodology. The comparison of predictions to measured error rates issued from radiation ground testing validates the proposed error rate prediction approach.

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DO - 10.1109/OLT.2002.1030194

M3 - Conference contribution

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BT - Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

PB - IEEE

CY - Piscataway, NJ

ER -

Bit flip injection in processor-based architectures: A case study

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