Bit flip injection in processor-based architectures: A case study

G.C. Cardarilli, F. Kaddour, A. Leandri, M. Ottavi, S. Pontarelli, R. Velazco

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

31 Citations (Scopus)


This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line "injection" and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral level processor description; being based on the so-called "saboteurs" method. Results obtained for benchmark programs executed by a widely used commercial 8-bit microprocessor, allow to validate both approaches which provide inputs for an original error rate prediction methodology. The comparison of predictions to measured error rates issued from radiation ground testing validates the proposed error rate prediction approach.
Original languageEnglish
Title of host publicationProceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002
Place of PublicationPiscataway, NJ
Number of pages11
ISBN (Print)0-7695-1641-6
Publication statusPublished - 2002
Externally publishedYes


Dive into the research topics of 'Bit flip injection in processor-based architectures: A case study'. Together they form a unique fingerprint.

Cite this