This paper presents the principles of two different approaches for the study of the effect of transient bit flips on the behavior of processor-based digital architectures: one of them based on the on-line "injection" and execution of pieces of code (called CEU codes) using a suitable hardware architecture, while the other is performed using a behavioral level processor description; being based on the so-called "saboteurs" method. Results obtained for benchmark programs executed by a widely used commercial 8-bit microprocessor, allow to validate both approaches which provide inputs for an original error rate prediction methodology. The comparison of predictions to measured error rates issued from radiation ground testing validates the proposed error rate prediction approach.
|Title of host publication||Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002|
|Place of Publication||Piscataway, NJ|
|Number of pages||11|
|Publication status||Published - 2002|