This paper focuses on data structures for multi-core reachability, which is a key component in model checking algorithms and other verification methods. A cornerstone of an efficient solution is the storage of visited states. In related work, static partitioning of the state space was combined with thread-local storage. This solution leaves room for improvements. This paper presents a solution with a shared state storage. It is based on a lockless hash table implementation and exhibits excellent scalability. The solution is specifically designed for the cache architecture of modern processors. Since model checking algorithms impose loose requirements on the hash table operations, their design can be streamlined substantially compared to related work on hash tables. The resulting speedups are analyzed and compared with related tools. Our implementation outperforms two state-of-the-art multi-core model checkers, SPIN (first presented at FMCAD 2006) and DiVinE, by a substantial margin while placing fewer constraints on the load balancing and search algorithms.
|Title of host publication||Proceedings of the 10th International Conference on Formal Methods in Computer-Aided Design|
|Editors||N. Sharygina, R. Bloem|
|Place of Publication||USA|
|Publisher||IEEE Computer Society|
|Number of pages||9|
|Publication status||Published - 20 Oct 2010|
- Model Checking
- hash tables
Laarman, A., van de Pol, J. C., & Weber, M. (2010). Boosting Multi-Core Reachability Performance with Shared Hash Tables. In N. Sharygina, & R. Bloem (Eds.), Proceedings of the 10th International Conference on Formal Methods in Computer-Aided Design (pp. 247-256). USA: IEEE Computer Society.