Bridging the Testing Speed Gap: Design for Delay Testability

H. Speek, Hans G. Kerkhoff, M. Sachdev, M. Shashaani

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    Abstract

    The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed
    Original languageUndefined
    Title of host publicationProceedings of IEEE European Test Workshop
    Place of PublicationCascais - Portugal
    PublisherIEEE
    Pages3-8
    ISBN (Print)0769507018
    DOIs
    Publication statusPublished - 27 Jan 2000
    EventIEEE European Test Workshop, 2000 - Cascais, Portugal
    Duration: 23 May 200026 May 2000

    Publication series

    Name
    PublisherIEEE

    Workshop

    WorkshopIEEE European Test Workshop, 2000
    Period23/05/0026/05/00
    Other23-26 May 2000

    Keywords

    • IR-16137
    • METIS-113022

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