@inproceedings{e06b04842bfd40c790764a2a9a8bb6cc,
title = "Bridging the Testing Speed Gap: Design for Delay Testability",
abstract = "The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed",
keywords = "IR-16137, METIS-113022",
author = "H. Speek and Kerkhoff, {Hans G.} and M. Sachdev and M. Shashaani",
year = "2000",
month = jan,
day = "27",
doi = "10.1109/ETW.2000.873771",
language = "Undefined",
isbn = "0769507018",
publisher = "IEEE",
pages = "3--8",
booktitle = "Proceedings of IEEE European Test Workshop",
address = "United States",
note = "IEEE European Test Workshop, 2000 ; Conference date: 23-05-2000 Through 26-05-2000",
}