Bridging the Testing Speed Gap: Design for Delay Testability

H. Speek, Hans G. Kerkhoff, M. Sachdev, M. Shashaani

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    31 Downloads (Pure)

    Abstract

    The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a design for delay testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. Also extensions for possible full BIST of delay faults are addressed
    Original languageUndefined
    Title of host publicationProceedings of IEEE European Test Workshop
    Place of PublicationCascais - Portugal
    PublisherIEEE
    Pages3-8
    ISBN (Print)0769507018
    DOIs
    Publication statusPublished - 27 Jan 2000

    Publication series

    Name
    PublisherIEEE

    Keywords

    • IR-16137
    • METIS-113022

    Cite this

    Speek, H., Kerkhoff, H. G., Sachdev, M., & Shashaani, M. (2000). Bridging the Testing Speed Gap: Design for Delay Testability. In Proceedings of IEEE European Test Workshop (pp. 3-8). Cascais - Portugal: IEEE. https://doi.org/10.1109/ETW.2000.873771