Buffer sizing to reduce interference and increase throughput of real-time stream processing applications

Existing temporal analysis and buffer sizing techniques for real-time stream processing applications ignore that FIFO buffers bound interference between tasks on the same processor. By considering this effect it can be shown that a reduction of buffer capacities can result in a higher throughput. However, the relation between buffer capacities and throughput is non-monotone in general, which makes an exploitation of the effect challenging. In this paper a buffer sizing approach is presented which exploits that FIFO buffers bound interference between tasks on shared processors. The approach combines temporal analysis using a cyclic dataflow model with computation of buffer capacities in an iterative manner and thereby enables higher throughput guarantees at smaller buffer capacities. It is shown that convergence of the proposed analysis flow is guaranteed. The benefits of the presented approach are demonstrated using a WLAN 802.11p transceiver application executed on a multiprocessor system with shared processors. If buffers without blocking writes are used an up to 25% higher guaranteeable throughput and up to 23% smaller buffer capacities can be determined compared to existing approaches. For systems using buffers with blocking writes the guaranteeable throughput is even up to 43% higher and buffer capacities up to 11% smaller.