Built-In Self-Test Methodology for A/D Converters

R. de Vries; T. Zwemstra; E.M.J.G. Bruis; P.P.L. Regtien

doi:10.1109/EDTC.1997.582382

Built-In Self-Test Methodology for A/D Converters

R. de Vries, T. Zwemstra, E.M.J.G. Bruis, P.P.L. Regtien

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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Abstract

A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a "full" BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique

Original language	English
Title of host publication	Proceedings of the European Design & Test Conference ED&TC97
Place of Publication	Paris, France
Pages	353-358
DOIs	https://doi.org/10.1109/EDTC.1997.582382
Publication status	Published - 17 Mar 1997
Event	European Design & Test Conference, ED&TC 1997 : ED&TC - Paris, France Duration: 17 Mar 1997 → 20 Mar 1997

Conference

Conference	European Design & Test Conference, ED&TC 1997
Country/Territory	France
City	Paris
Period	17/03/97 → 20/03/97

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Vries97builtFinal published version, 548 KB

Cite this

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title = "Built-In Self-Test Methodology for A/D Converters",

abstract = "A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a {"}full{"} BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique",

author = "{de Vries}, R. and T. Zwemstra and E.M.J.G. Bruis and P.P.L. Regtien",

year = "1997",

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note = "European Design & Test Conference, ED&TC 1997<br/> : ED&TC ; Conference date: 17-03-1997 Through 20-03-1997",

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AU - de Vries, R.

AU - Zwemstra, T.

AU - Bruis, E.M.J.G.

AU - Regtien, P.P.L.

PY - 1997/3/17

Y1 - 1997/3/17

N2 - A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a "full" BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique

AB - A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a "full" BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique

U2 - 10.1109/EDTC.1997.582382

DO - 10.1109/EDTC.1997.582382

M3 - Conference contribution

SN - 9780818677861

SP - 353

EP - 358

BT - Proceedings of the European Design & Test Conference ED&TC97

CY - Paris, France

T2 - European Design & Test Conference, ED&TC 1997<br/>

Y2 - 17 March 1997 through 20 March 1997

ER -

Built-In Self-Test Methodology for A/D Converters

Abstract

Conference

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