Bulk-Si FinFET technology for ultra-high aspect-ratio devices

Vladimir Jovanovic; Lis K. Nanver; Tomislav Suligoj; Mirko Poljak

doi:10.1109/ESSDERC.2009.5331554

Bulk-Si FinFET technology for ultra-high aspect-ratio devices

Vladimir Jovanovic^*, Lis K. Nanver, Tomislav Suligoj, Mirko Poljak

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

FinFETs with 1 μm tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls .

Original language	English
Title of host publication	ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
Pages	241-244
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2009.5331554
Publication status	Published - 1 Dec 2009
Externally published	Yes
Event	39th European Solid-State Device Research Conference, ESSDERC 2009 - Athens, Greece Duration: 14 Sept 2009 → 18 Sept 2009

Conference

Conference	39th European Solid-State Device Research Conference, ESSDERC 2009
Abbreviated title	ESSDERC 2009
Country/Territory	Greece
City	Athens
Period	14/09/09 → 18/09/09

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10.1109/ESSDERC.2009.5331554

Cite this

@inproceedings{14b1c1b116df4601980bd6c75628a985,

title = "Bulk-Si FinFET technology for ultra-high aspect-ratio devices",

abstract = "FinFETs with 1 μm tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls .",

author = "Vladimir Jovanovic and Nanver, {Lis K.} and Tomislav Suligoj and Mirko Poljak",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ESSDERC.2009.5331554",

language = "English",

isbn = "9781424443536",

pages = "241--244",

booktitle = "ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference",

note = "39th European Solid-State Device Research Conference, ESSDERC 2009, ESSDERC 2009 ; Conference date: 14-09-2009 Through 18-09-2009",

}

Jovanovic, V, Nanver, LK, Suligoj, T & Poljak, M 2009, Bulk-Si FinFET technology for ultra-high aspect-ratio devices. in ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference., 5331554, pp. 241-244, 39th European Solid-State Device Research Conference, ESSDERC 2009, Athens, Greece, 14/09/09. https://doi.org/10.1109/ESSDERC.2009.5331554

TY - GEN

T1 - Bulk-Si FinFET technology for ultra-high aspect-ratio devices

AU - Jovanovic, Vladimir

AU - Nanver, Lis K.

AU - Suligoj, Tomislav

AU - Poljak, Mirko

PY - 2009/12/1

Y1 - 2009/12/1

N2 - FinFETs with 1 μm tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls .

AB - FinFETs with 1 μm tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls .

UR - http://www.scopus.com/inward/record.url?scp=72849121250&partnerID=8YFLogxK

U2 - 10.1109/ESSDERC.2009.5331554

DO - 10.1109/ESSDERC.2009.5331554

M3 - Conference contribution

AN - SCOPUS:72849121250

SN - 9781424443536

SP - 241

EP - 244

BT - ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

T2 - 39th European Solid-State Device Research Conference, ESSDERC 2009

Y2 - 14 September 2009 through 18 September 2009

ER -

Bulk-Si FinFET technology for ultra-high aspect-ratio devices

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