Bulk-Si FinFET technology for ultra-high aspect-ratio devices

Vladimir Jovanovic*, Lis K. Nanver, Tomislav Suligoj, Mirko Poljak

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)

Abstract

FinFETs with 1 μm tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins and a height of the active part of the fin up to 650 nm have been fabricated and demonstrate the scaling potentials of the proposed technology. This extreme reduction of the fin width degrades electron mobility as compared to devices with 15-nm-wide fins, which have been used here to investigate the current conduction capability of FinFETs with (111) sidewalls .

Original languageEnglish
Title of host publicationESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
Pages241-244
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2009
Externally publishedYes
Event39th European Solid-State Device Research Conference, ESSDERC 2009 - Athens, Greece
Duration: 14 Sep 200918 Sep 2009

Conference

Conference39th European Solid-State Device Research Conference, ESSDERC 2009
Abbreviated titleESSDERC 2009
CountryGreece
CityAthens
Period14/09/0918/09/09

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    Jovanovic, V., Nanver, L. K., Suligoj, T., & Poljak, M. (2009). Bulk-Si FinFET technology for ultra-high aspect-ratio devices. In ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference (pp. 241-244). [5331554] https://doi.org/10.1109/ESSDERC.2009.5331554