CeO2 and HfO2 high-k gate dielectrics by pulsed laser deposition: from binary oxides to nanolaminates

Since the early years of integrated circuit (IC) technology, the complexity of the IC devices has increased continuously as predicted by the famous Moore's Law. As of 2006, most of the central processing units are produced at 90 nm level and even 65 nm devices are recently introduced. The thickness of the gate dielectric is also decreased accordingly for a good channel control, which can be defined by the terms of gate capacitance. The thickness of the state of the art dielectrics are below the direct tunneling limit and doesn't meet the near future gate leakage requirements defined in the International Technology Roadmap for Semiconductors. High-k gate dielectrics are introduced as a solution for overcoming the gate leakage problem by maintaining the same gate capacitance levels with larger physical thicknesses.

In the search for a high-k material Pulsed Laser Deposition is one of the most powerful tools. It has a number of advantages like independent control of process parameters, layer control in the atomic level, ability of using multiple target materials for multilayer depositions and fast process compared to the other deposition methods, which make PLD an attractive tool for materials research.

In this thesis, PLD is used for deposition of CeO2 and HfO2 layers. Different processing conditions were investigated from oxidizing to reducing ambient deposition, in-situ post deposition anneal and deposition of binary oxide layers, as well as the nanolaminates. The electrical and structural properties of the deposited layers were characterized and the links between these properties were tried to be established.