Channel Communication and Reconfigurable Hardware

Many applications can be structured as a set of processes or threads that communicate via channels. These threads can be executed on various platforms (e.g. general purpose CPU, DSP, FPGA, etc). In our research we apply channels as a basic communication mechanism between threads in a reconfigurable system. The research involves providing system level functions to describe the setup of communicating threads, which may now either run timeshared on a general CPU or in dynamically-setup special purpose logic that runs on reconfigurable hardware. The use of channels and threads running in both software and hardware, will be made transparent for the application level programmers by the system level functions. By first describing the threads and how they are connected and then letting the operating system decide on 'geographical' placement of the threads and buffers, multiprogramming will be supported and programs will be able to run on different setups of hardware (i.e. different amount of CPUs or available programmable logic). This is an ongoing work, the paper is a collection of thoughts, which lead to a first setup of rudimentary support functions in the operating system.