Channel formation for 0.15 μm CMOS using through-the-gate implantation

A.H. Montree; Y.V. Ponomarev; W.M. Baks; A.C.M.C. van Brandenburg; C. Dachs; R.F.M. Roes; J. Schmitz; P.A. Stolk; H.P. Tuinhout

doi:10.1109/VTSA.1999.785987

Channel formation for 0.15 μm CMOS using through-the-gate implantation

A.H. Montree, Y.V. Ponomarev, W.M. Baks, A.C.M.C. van Brandenburg, C. Dachs, R.F.M. Roes, J. Schmitz, P.A. Stolk, H.P. Tuinhout

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

19 Downloads (Pure)

Abstract

Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained.

Original language	English
Title of host publication	1999 International Symposium on VLSI Technology, Systems, and Applications
Subtitle of host publication	proceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	10-13
Number of pages	4
ISBN (Print)	0-7803-5620-9
DOIs	https://doi.org/10.1109/VTSA.1999.785987
Publication status	Published - 10 Jun 1999
Externally published	Yes
Event	1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei International Convention Center, Taipei, Taiwan Duration: 8 Jun 1999 → 10 Jun 1999

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications: Proceedings
Publisher	IEEE
Volume	1999
ISSN (Print)	1524-766X

Conference

Conference	1999 International Symposium on VLSI Technology, Systems, and Applications
Country/Territory	Taiwan
City	Taipei
Period	8/06/99 → 10/06/99

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10.1109/VTSA.1999.785987

Channel formation for 0.15µm CMOS using Through-the-Gate ImplantationSubmitted version, 214 KBLicence: Unspecified

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Montree, A. H., Ponomarev, Y. V., Baks, W. M., van Brandenburg, A. C. M. C., Dachs, C., Roes, R. F. M., Schmitz, J., Stolk, P. A., & Tuinhout, H. P. (1999). Channel formation for 0.15 μm CMOS using through-the-gate implantation. In 1999 International Symposium on VLSI Technology, Systems, and Applications: proceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C (pp. 10-13). (International Symposium on VLSI Technology, Systems, and Applications: Proceedings; Vol. 1999). IEEE. https://doi.org/10.1109/VTSA.1999.785987

Montree, A.H. ; Ponomarev, Y.V. ; Baks, W.M. et al. / Channel formation for 0.15 μm CMOS using through-the-gate implantation. 1999 International Symposium on VLSI Technology, Systems, and Applications: proceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C. Piscataway, NJ : IEEE, 1999. pp. 10-13 (International Symposium on VLSI Technology, Systems, and Applications: Proceedings).

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abstract = "Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained.",

author = "A.H. Montree and Y.V. Ponomarev and W.M. Baks and {van Brandenburg}, A.C.M.C. and C. Dachs and R.F.M. Roes and J. Schmitz and P.A. Stolk and H.P. Tuinhout",

year = "1999",

month = jun,

day = "10",

doi = "10.1109/VTSA.1999.785987",

language = "English",

isbn = "0-7803-5620-9",

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publisher = "IEEE",

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note = "1999 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 08-06-1999 Through 10-06-1999",

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Montree, AH, Ponomarev, YV, Baks, WM, van Brandenburg, ACMC, Dachs, C, Roes, RFM, Schmitz, J, Stolk, PA & Tuinhout, HP 1999, Channel formation for 0.15 μm CMOS using through-the-gate implantation. in 1999 International Symposium on VLSI Technology, Systems, and Applications: proceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C. International Symposium on VLSI Technology, Systems, and Applications: Proceedings, vol. 1999, IEEE, Piscataway, NJ, pp. 10-13, 1999 International Symposium on VLSI Technology, Systems, and Applications, Taipei, Taiwan, 8/06/99. https://doi.org/10.1109/VTSA.1999.785987

Channel formation for 0.15 μm CMOS using through-the-gate implantation. / Montree, A.H.; Ponomarev, Y.V.; Baks, W.M. et al.
1999 International Symposium on VLSI Technology, Systems, and Applications: proceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C. Piscataway, NJ: IEEE, 1999. p. 10-13 (International Symposium on VLSI Technology, Systems, and Applications: Proceedings; Vol. 1999).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Channel formation for 0.15 μm CMOS using through-the-gate implantation

AU - Montree, A.H.

AU - Ponomarev, Y.V.

AU - Baks, W.M.

AU - van Brandenburg, A.C.M.C.

AU - Dachs, C.

AU - Roes, R.F.M.

AU - Schmitz, J.

AU - Stolk, P.A.

AU - Tuinhout, H.P.

PY - 1999/6/10

Y1 - 1999/6/10

N2 - Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained.

AB - Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained.

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BT - 1999 International Symposium on VLSI Technology, Systems, and Applications

PB - IEEE

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T2 - 1999 International Symposium on VLSI Technology, Systems, and Applications

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ER -

Montree AH, Ponomarev YV, Baks WM, van Brandenburg ACMC, Dachs C, Roes RFM et al. Channel formation for 0.15 μm CMOS using through-the-gate implantation. In 1999 International Symposium on VLSI Technology, Systems, and Applications: proceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C. Piscataway, NJ: IEEE. 1999. p. 10-13. (International Symposium on VLSI Technology, Systems, and Applications: Proceedings). doi: 10.1109/VTSA.1999.785987

Channel formation for 0.15 μm CMOS using through-the-gate implantation

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