Channel formation for 0.15 μm CMOS using through-the-gate implantation

A.H. Montree, Y.V. Ponomarev, W.M. Baks, A.C.M.C. van Brandenburg, C. Dachs, R.F.M. Roes, J. Schmitz, P.A. Stolk, H.P. Tuinhout

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)
3 Downloads (Pure)

Abstract

Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained.

Original languageEnglish
Title of host publication1999 International Symposium on VLSI Technology, Systems, and Applications
Subtitle of host publicationproceedings of technical papers, June 8-10, 1999, Taipei International Convention Center, Taipei, Taiwan, R.O.C
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages10-13
Number of pages4
ISBN (Print)0-7803-5620-9
DOIs
Publication statusPublished - 10 Jun 1999
Externally publishedYes
Event1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei International Convention Center, Taipei, Taiwan, Province of China
Duration: 8 Jun 199910 Jun 1999

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications: Proceedings
PublisherIEEE
Volume1999
ISSN (Print)1524-766X

Conference

Conference1999 International Symposium on VLSI Technology, Systems, and Applications
CountryTaiwan, Province of China
CityTaipei
Period8/06/9910/06/99

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