Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

Y.V. Ponomarev; P.A. Stolk; A.C.M.C. van Brandenburg; R. Roes; A.H. Montree; J. Schmitz; P.H. Woerlee

doi:10.1109/IEDM.1998.746438

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

Y.V. Ponomarev, P.A. Stolk, A.C.M.C. van Brandenburg, R. Roes, A.H. Montree, J. Schmitz, P.H. Woerlee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

21 Citations (Scopus)

252 Downloads (Pure)

Abstract

A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

Original language	English
Title of host publication	International Electron Devices Meeting 1998
Subtitle of host publication	San Francisco, CA, December 6-9, 1998, IEDM technical digest
Publisher	IEEE
Pages	635-638
Number of pages	4
ISBN (Print)	0-7803-4774-9, 0-7803-4776-5
DOIs	https://doi.org/10.1109/IEDM.1998.746438
Publication status	Published - 1 Dec 1998
Event	1998 IEEE International Electron Devices Meeting - San Francisco, United States Duration: 6 Dec 1998 → 9 Dec 1998

Publication series

Name	International Electron Devices Meeting, IEDM Technical Digest
Publisher	IEEE
Volume	1998
ISSN (Print)	0163-1918

Conference

Conference	1998 IEEE International Electron Devices Meeting
Country/Territory	United States
City	San Francisco
Period	6/12/98 → 9/12/98

Access to Document

10.1109/IEDM.1998.746438

Channel Profile Engineering of 0,1µm-Si MOSFETs by Though-the-Gate ImplantationSubmitted version, 282 KBLicence: Unspecified

Cite this

Ponomarev, Y. V., Stolk, P. A., van Brandenburg, A. C. M. C., Roes, R., Montree, A. H., Schmitz, J., & Woerlee, P. H. (1998). Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation. In International Electron Devices Meeting 1998 : San Francisco, CA, December 6-9, 1998, IEDM technical digest (pp. 635-638). (International Electron Devices Meeting, IEDM Technical Digest; Vol. 1998). IEEE. https://doi.org/10.1109/IEDM.1998.746438

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title = "Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation",

abstract = "A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.",

author = "Y.V. Ponomarev and P.A. Stolk and {van Brandenburg}, A.C.M.C. and R. Roes and A.H. Montree and J. Schmitz and P.H. Woerlee",

year = "1998",

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doi = "10.1109/IEDM.1998.746438",

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series = "International Electron Devices Meeting, IEDM Technical Digest",

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Ponomarev, YV, Stolk, PA, van Brandenburg, ACMC, Roes, R, Montree, AH, Schmitz, J & Woerlee, PH 1998, Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation. in International Electron Devices Meeting 1998 : San Francisco, CA, December 6-9, 1998, IEDM technical digest. International Electron Devices Meeting, IEDM Technical Digest, vol. 1998, IEEE, pp. 635-638, 1998 IEEE International Electron Devices Meeting, San Francisco, California, United States, 6/12/98. https://doi.org/10.1109/IEDM.1998.746438

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation. / Ponomarev, Y.V.; Stolk, P.A.; van Brandenburg, A.C.M.C. et al.
International Electron Devices Meeting 1998 : San Francisco, CA, December 6-9, 1998, IEDM technical digest. IEEE, 1998. p. 635-638 (International Electron Devices Meeting, IEDM Technical Digest; Vol. 1998).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - A novel approach to the SSR channel profile formation for MOSFETs is suggested, with dopant implantation in the late stages of the processing, with the gate, source/drain already in (`TGi'). Only a single damage/activation anneal and the back-end thermal budget are experienced by the implanted dopants, which results in steep profiles even when light boron ions are used. High-performance NMOS devices with excellent SCE control designed for low-voltage digital, analog and RF operation were realized using this technique. For PMOS the use of TGi is restricted by significant diffusion of source/drain extensions due to the TGi damage induced TED.

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Ponomarev YV, Stolk PA, van Brandenburg ACMC, Roes R, Montree AH, Schmitz J et al. Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation. In International Electron Devices Meeting 1998 : San Francisco, CA, December 6-9, 1998, IEDM technical digest. IEEE. 1998. p. 635-638. (International Electron Devices Meeting, IEDM Technical Digest). doi: 10.1109/IEDM.1998.746438

Channel profile engineering of 0.1 μm-Si MOSFETs by through-the-gate implantation

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