Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it is still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition. As these failures could be related to the memory cell's ability to retain its stored charge, an empirical characterization of DRAM data retention time was performed within this study. Retention time information was collected from SDRAM devices from two different vendors to evaluate the impact of four different factors (temperature, data background, previous charge level and variable retention time) on DRAM cells retention time. Gathered results can be useful in defining enhanced test procedures for the early detection of data retention faults.
|Title of host publication||Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems|
|Publication status||Published - 2014|
|Event||International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, Netherlands|
Duration: 1 Oct 2014 → 3 Oct 2014
|Conference||International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014|
|Abbreviated title||DFT 2014|
|Period||1/10/14 → 3/10/14|