Abstract
Low energy boron implants between 200 eV and 10 keV have been characterized for the effect of channelling and of pre-amorphization on the as-implanted profiles. Suitable rapid thermal anneal conditions for a shallow drain formation compatible with a 0.18 μm CMOS process were determined. One of these conditions was then used to fabricate PMOS transistors with shallow drain extensions using a 0.18 μm flow chart. Transistor characteristics such as threshold voltage, junction leakage and asymmetry were then measured as a function of implanted species and energy, and of gate length.
Original language | English |
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Title of host publication | Ion implantation technology-98 |
Subtitle of host publication | 1998 International Conference on Ion Implantation Technology proceedings, Kyoto, Japan, June 22-26, 1998 |
Editors | J. Matsuo, G. Takaoka, I. Yamada |
Publisher | IEEE |
Pages | 905-908 |
Number of pages | 4 |
Volume | 2 |
ISBN (Print) | 0-7803-4538-X, 0-7803-4539-8 |
DOIs | |
Publication status | Published - 1 Dec 1999 |
Externally published | Yes |
Event | 1998 International Conference on Ion Implantation Technology, IIT 1998 - Kyoto, Japan Duration: 22 Jun 1998 → 26 Jun 1998 |
Conference
Conference | 1998 International Conference on Ion Implantation Technology, IIT 1998 |
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Abbreviated title | ITT |
Country/Territory | Japan |
City | Kyoto |
Period | 22/06/98 → 26/06/98 |