Charge transport in nanoscale lateral and vertical organic semiconductor devices

Bojian Xu

Research output: ThesisPhD Thesis - Research UT, graduation UT

464 Downloads (Pure)


Organic semiconductors have been drawing more and more attention due to their huge potential for low-cost, flexible, printable electronics and spintronics. In this thesis research, we have investigated charge transport in two organic semiconductors, DXP and P3HT, in different device configurations. Chapter 1 provides a motivation for our work and the thesis outline. Chapter 2 concisely discusses the theoretical background related to the thesis research. In Chapter 3, we introduce a device fabrication process based on the nanoindentation technique using AFM to embed DXP-loaded zeolite L crystals into devices for electrical transport measurements. We present a nanoindentation technique which is able to create holes on top of the zeolite crystals with ~150 - 300 nm diameters. We also investigated the charge transport properties of the DXP lateral field-effect transistors made by drop-casting DXP onto interdigitated Au electrodes, as reported in Chapter 4. The DXP lateral field-effect transistors exhibit n-type channel behavior based on the output and transfer characteristics. In Chapter 5, we present a novel fabrication method by which two-terminal vertical P3HT junctions with ultrathin (100 to 5 nm) P3HT films can be realized. The 5 nm thick P3HT junctions carry very high current density, up to 106 A/m2. The measured temperature dependence reveal thermally assisted hopping transport. Simulation of the temperature dependence has been performed based on the drift-diffusion model with a Gaussian density of states. The simulated results indicate a low injection barrier (less than 0.1 eV), which can explain the weaker temperature dependence of the devices with thinner P3HT. Follow up on this work, we have investigated gated vertical P3HT pillar devices in Chapter 6. The measured electrical transport results do not show a distinct gate effect. ATLAS device simulations show not only a distinct gate effect, but also a larger drain current than in the experiment. We propose that a damaged layer at the edge of the P3HT pillars could be the reason for the reduction of the gate effect and conductivity. In Chapter 7 we provide a general discussion of the results obtained in this thesis, and give an outlook for future research.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • University of Twente
  • van der Wiel, Wilfred G., Supervisor
Award date10 Mar 2017
Place of PublicationEnschede
Print ISBNs978-90-365-4286-9
Publication statusPublished - 10 Mar 2017


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