Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

J. Van Zoeren, L. K. Nanver

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.

Original languageEnglish
Title of host publication2022 IEEE 34th International Conference on Microelectronic Test Structures, ICMTS 2022 - Proceedings
PublisherIEEE
Pages149-154
Number of pages6
ISBN (Electronic)978-1-6654-8565-1
DOIs
Publication statusPublished - 26 Sep 2022
Event34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022 - Crown Plaza Cleveland at Playhouse Square, Cleveland, United States
Duration: 21 Mar 202215 Apr 2022

Conference

Conference34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022
Country/TerritoryUnited States
CityCleveland
Period21/03/2215/04/22

Keywords

  • 2-D interfacial layers
  • current-voltage characteristics
  • diodes
  • lateral bipolar transistor
  • temperature dependent measurements
  • 22/4 OA procedure

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