Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

J. Van Zoeren; L. K. Nanver

doi:10.1109/ICMTS50340.2022.9898239

Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.

Original language	English
Title of host publication	2022 IEEE 34th International Conference on Microelectronic Test Structures, ICMTS 2022 - Proceedings
Publisher	IEEE
Pages	149-154
Number of pages	6
ISBN (Electronic)	978-1-6654-8565-1
DOIs	https://doi.org/10.1109/ICMTS50340.2022.9898239
Publication status	Published - 26 Sep 2022
Event	34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022 - Crown Plaza Cleveland at Playhouse Square, Cleveland, United States Duration: 21 Mar 2022 → 15 Apr 2022

Conference

Conference	34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022
Country/Territory	United States
City	Cleveland
Period	21/03/22 → 15/04/22

Keywords

2-D interfacial layers
current-voltage characteristics
diodes
lateral bipolar transistor
temperature dependent measurements
22/4 OA procedure

Access to Document

10.1109/ICMTS50340.2022.9898239

Cite this

@inproceedings{835ea7c057344b57923ca3191201bcea,

title = "Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers",

abstract = "Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced. ",

keywords = "2-D interfacial layers, current-voltage characteristics, diodes, lateral bipolar transistor, temperature dependent measurements, 22/4 OA procedure",

author = "{Van Zoeren}, J. and Nanver, {L. K.}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022 ; Conference date: 21-03-2022 Through 15-04-2022",

year = "2022",

month = sep,

day = "26",

doi = "10.1109/ICMTS50340.2022.9898239",

language = "English",

pages = "149--154",

booktitle = "2022 IEEE 34th International Conference on Microelectronic Test Structures, ICMTS 2022 - Proceedings",

publisher = "IEEE",

address = "United States",

}

Van Zoeren, J & Nanver, LK 2022, Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers. in 2022 IEEE 34th International Conference on Microelectronic Test Structures, ICMTS 2022 - Proceedings. IEEE, pp. 149-154, 34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022, Cleveland, Ohio, United States, 21/03/22. https://doi.org/10.1109/ICMTS50340.2022.9898239

Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers. / Van Zoeren, J.; Nanver, L. K.

2022 IEEE 34th International Conference on Microelectronic Test Structures, ICMTS 2022 - Proceedings. IEEE, 2022. p. 149-154.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

AU - Van Zoeren, J.

AU - Nanver, L. K.

PY - 2022/9/26

Y1 - 2022/9/26

N2 - Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.

AB - Two hole-current extraction methods are discussed as potential checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers on n-substrates. Both methods are unaffected by leakage currents related to defects near the junction. The one method is commonly used: the slope of the collector current in a lateral pnp Gummel plot is determined. The validity of this method is limited by series resistance and Early-voltage/punch-through effects related to depletion of the base region. The other method applies a differential measurement to determine a hole spreading current with an ideal slope. This method is not limited by depletion width variations but if the electron-to-hole current-ratio is too high, detrimental parasitic electron currents are induced.

KW - 2-D interfacial layers

KW - current-voltage characteristics

KW - diodes

KW - lateral bipolar transistor

KW - temperature dependent measurements

KW - 22/4 OA procedure

UR - http://www.scopus.com/inward/record.url?scp=85139836297&partnerID=8YFLogxK

U2 - 10.1109/ICMTS50340.2022.9898239

DO - 10.1109/ICMTS50340.2022.9898239

M3 - Conference contribution

AN - SCOPUS:85139836297

SP - 149

EP - 154

BT - 2022 IEEE 34th International Conference on Microelectronic Test Structures, ICMTS 2022 - Proceedings

PB - IEEE

T2 - 34th IEEE International Conference on Microelectronic Test Structures, ICMTS 2022

Y2 - 21 March 2022 through 15 April 2022

ER -

Checks on temperature during on-wafer I-V characterization of Si diodes made with 2-D interfacial layers

Abstract

Conference

Keywords

Access to Document

Other files and links

Embargoed Document

Fingerprint

Cite this