Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits

Richard Rosing, Andrew M.D. Richardson, Yassine Eben Aimine, Hans G. Kerkhoff, Antonia J. Acosta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)
    1 Downloads (Pure)


    Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults.
    Original languageEnglish
    Title of host publicationProceedings of the 1998 IEEE International Workshop on IDDQ Testing
    Subtitle of host publicationNovember 12-13,1998, San Jose, California
    EditorsYashwant K. Malaiya, Sankaran M. Menon
    Place of PublicationPiscataway, NJ
    Number of pages6
    ISBN (Electronic)0-8 186-9193-X
    ISBN (Print)0-8186-9191-3
    Publication statusPublished - 27 May 1998
    EventIEEE International Workshop on IDDQ Testing 1998 - San Jose, United States
    Duration: 12 Nov 199813 Nov 1998


    ConferenceIEEE International Workshop on IDDQ Testing 1998
    Country/TerritoryUnited States
    CitySan Jose


    • Circuit testing
    • Clocks
    • Switching circuits
    • Logic testing
    • Discrete cosine transforms
    • Logic circuits
    • Circuit faults
    • Threshold voltage
    • Frequency
    • Performance evaluation


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