Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits

Richard Rosing; Andrew M.D. Richardson; Yassine Eben Aimine; Hans G. Kerkhoff; Antonia J. Acosta

doi:10.1109/IDDQ.1998.730727

Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits

Richard Rosing, Andrew M.D. Richardson, Yassine Eben Aimine, Hans G. Kerkhoff, Antonia J. Acosta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

2 Downloads (Pure)

Abstract

Using an I_ddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of I_ddq testability and a reduced test vector set for the detection of bridging faults.

Original language	English
Title of host publication	Proceedings of the 1998 IEEE International Workshop on IDDQ Testing
Subtitle of host publication	November 12-13,1998, San Jose, California
Editors	Yashwant K. Malaiya, Sankaran M. Menon
Place of Publication	Piscataway, NJ
Publisher	IEEE
Number of pages	6
ISBN (Electronic)	0-8 186-9193-X
ISBN (Print)	0-8186-9191-3
DOIs	https://doi.org/10.1109/IDDQ.1998.730727
Publication status	Published - 27 May 1998
Event	IEEE International Workshop on IDDQ Testing 1998 - San Jose, United States Duration: 12 Nov 1998 → 13 Nov 1998

Conference

Conference	IEEE International Workshop on IDDQ Testing 1998
Country/Territory	United States
City	San Jose
Period	12/11/98 → 13/11/98

Keywords

Circuit testing
Clocks
Switching circuits
Logic testing
Discrete cosine transforms
Logic circuits
Circuit faults
Threshold voltage
Frequency
Performance evaluation

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10.1109/IDDQ.1998.730727

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Rosing, R., Richardson, A. M. D., Aimine, Y. E., Kerkhoff, H. G., & Acosta, A. J. (1998). Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits. In Y. K. Malaiya, & S. M. Menon (Eds.), Proceedings of the 1998 IEEE International Workshop on IDDQ Testing: November 12-13,1998, San Jose, California IEEE. https://doi.org/10.1109/IDDQ.1998.730727

@inproceedings{1ce9c78f88ca48c9bd04f0645fb16247,

title = "Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits",

abstract = "Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults.",

keywords = "Circuit testing, Clocks, Switching circuits, Logic testing, Discrete cosine transforms, Logic circuits, Circuit faults, Threshold voltage, Frequency, Performance evaluation",

author = "Richard Rosing and Richardson, {Andrew M.D.} and Aimine, {Yassine Eben} and Kerkhoff, {Hans G.} and Acosta, {Antonia J.}",

year = "1998",

month = may,

day = "27",

doi = "10.1109/IDDQ.1998.730727",

language = "English",

isbn = "0-8186-9191-3",

editor = "Malaiya, {Yashwant K.} and Menon, {Sankaran M.}",

booktitle = "Proceedings of the 1998 IEEE International Workshop on IDDQ Testing",

publisher = "IEEE",

address = "United States",

note = "IEEE International Workshop on IDDQ Testing 1998 ; Conference date: 12-11-1998 Through 13-11-1998",

}

Rosing, R, Richardson, AMD, Aimine, YE, Kerkhoff, HG & Acosta, AJ 1998, Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits. in YK Malaiya & SM Menon (eds), Proceedings of the 1998 IEEE International Workshop on IDDQ Testing: November 12-13,1998, San Jose, California. IEEE, Piscataway, NJ, IEEE International Workshop on IDDQ Testing 1998, San Jose, California, United States, 12/11/98. https://doi.org/10.1109/IDDQ.1998.730727

Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits. / Rosing, Richard; Richardson, Andrew M.D.; Aimine, Yassine Eben et al.
Proceedings of the 1998 IEEE International Workshop on IDDQ Testing: November 12-13,1998, San Jose, California. ed. / Yashwant K. Malaiya; Sankaran M. Menon. Piscataway, NJ: IEEE, 1998.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Clock Switching

T2 - IEEE International Workshop on IDDQ Testing 1998

AU - Rosing, Richard

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AU - Aimine, Yassine Eben

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AU - Acosta, Antonia J.

PY - 1998/5/27

Y1 - 1998/5/27

N2 - Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults.

AB - Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults.

KW - Circuit testing

KW - Clocks

KW - Switching circuits

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KW - Discrete cosine transforms

KW - Logic circuits

KW - Circuit faults

KW - Threshold voltage

KW - Frequency

KW - Performance evaluation

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M3 - Conference contribution

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A2 - Malaiya, Yashwant K.

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PB - IEEE

CY - Piscataway, NJ

Y2 - 12 November 1998 through 13 November 1998

ER -

Clock Switching: A New Design for Current Testability (DcT) Method for Dynamic Logic Circuits

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Conference

Keywords

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