Abstract
Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults.
Original language | English |
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Title of host publication | Proceedings of the 1998 IEEE International Workshop on IDDQ Testing |
Subtitle of host publication | November 12-13,1998, San Jose, California |
Editors | Yashwant K. Malaiya, Sankaran M. Menon |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Number of pages | 6 |
ISBN (Electronic) | 0-8 186-9193-X |
ISBN (Print) | 0-8186-9191-3 |
DOIs | |
Publication status | Published - 27 May 1998 |
Event | IEEE International Workshop on IDDQ Testing 1998 - San Jose, United States Duration: 12 Nov 1998 → 13 Nov 1998 |
Conference
Conference | IEEE International Workshop on IDDQ Testing 1998 |
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Country | United States |
City | San Jose |
Period | 12/11/98 → 13/11/98 |
Keywords
- Circuit testing
- Clocks
- Switching circuits
- Logic testing
- Discrete cosine transforms
- Logic circuits
- Circuit faults
- Threshold voltage
- Frequency
- Performance evaluation