Abstract
In this paper we propose a novel two-dimensional clocking and timing scheme for systems which permit a reduction in the longest line length in each clocking zone. The proposed clocking schemes utilize logic propagation techniques which have been developed for systolic arrays. Placement of QCA cells is modified to ensure correct signal generation and timing. The significant reduction in the longest line length permits a fast timing and efficient pipelining to occur, while guaranteeing kink-free behavior in switching.
Original language | English |
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Title of host publication | 2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006 |
DOIs | |
Publication status | Published - 2006 |
Externally published | Yes |
Event | 6th IEEE Conference on Nanotechnology 2006 - Cincinnati, United States Duration: 17 Jul 2006 → 20 Jul 2006 Conference number: 6 |
Conference
Conference | 6th IEEE Conference on Nanotechnology 2006 |
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Country/Territory | United States |
City | Cincinnati |
Period | 17/07/06 → 20/07/06 |