Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency

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Abstract

At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1-2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed-array IC-architecture.
Original languageEnglish
Pages (from-to)693-703
Number of pages11
JournalIEEE journal of solid-state circuits
Volume50
Issue number3
DOIs
Publication statusPublished - 1 Mar 2015

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All-pass filters
Time delay
Electric delay lines
Transfer functions
Electric lines
Capacitors
Networks (circuits)

Keywords

  • EWI-25929
  • IR-95674
  • METIS-312548

Cite this

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title = "Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency",
abstract = "At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1-2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed-array IC-architecture.",
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Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency. / Garakoui, S.K.; Klumperink, Eric A.M.; Nauta, Bram; van Vliet, Frank Edward.

In: IEEE journal of solid-state circuits, Vol. 50, No. 3, 01.03.2015, p. 693-703.

Research output: Contribution to journalArticleAcademicpeer-review

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T1 - Compact cascadable gm-C all-pass true time delay cell with reduced delay variation over frequency

AU - Garakoui, S.K.

AU - Klumperink, Eric A.M.

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AU - van Vliet, Frank Edward

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AB - At low-GHz frequencies, analog time-delay cells realized by LC delay lines or transmission lines are unpractical in CMOS, due to their large size. As an alternative, delays can be approximated by all-pass filters exploiting transconductors and capacitors (g m -C filters). This paper presents an easily cascadable compact g m -C all-pass filter cell for 1-2.5 GHz. Compared to previous g m -RC and g m -C filter cells, it achieves at least 5x larger frequency range for the same relative delay variation, while keeping gain variation within 1 dB. This paper derives design equations for the transfer function and several non-idealities. Circuit techniques to improve phase linearity and reduce delay variation over frequency, are also proposed. A 160 nm CMOS chip with maximum delay of 550 ps is demonstrated with monotonous delay steps of 13 ps (41 steps) and an RMS delay variation error of less than 10 ps over more than an octave in frequency (1-2.5 GHz). The delay per area is at least 50x more than for earlier chips. The all-pass cells are used to realize a four element timed-array receiver IC. Measurement results of the beam pattern demonstrate the wideband operation capability of the g m -RC time delay cell and timed-array IC-architecture.

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