Comparing CλaSH and VHDL by implementing a dataflow processor

A. Niedermeier, Rinse Wester, Rinse Wester, C.P.R. Baaij, Jan Kuper, Gerardus Johannes Maria Smit

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    As embedded systems are becoming increasingly complex, the design process and verification have become very time-consuming. Additionally, specifying hardware manually in a low-level hardware description language like VHDL is usually an error-prone task. In our group, a tool (the ClaSH compiler) was developed to generate fully synthesisable VHDL code from a specification given in the functional programming language Haskell. In this paper, we present a comparison between two implementations of the same design by using ClaSH and hand-written VHDL. The design is a simple dataflow processor. As measures of interest area, performance, power consumption and source lines of code (SLOC) are used. The obtained results indicate that the ClaSH -generated VHDL code as well as the netlist after synthesis and place and route are functionally correct. The placed and routed hand-written VHDL code has also the correct behaviour. Furthermore, a similar performance is achieved. The power consumption is even lower for the ClaSH implementation. The SLOC for ClaSH is considerably smaller and it is possible to specify the design in a much higher level of abstraction compared to VHDL.
    Original languageUndefined
    Title of host publicationProceedings of the Workshop on PROGram for Research on Embedded Systems and Software (PROGRESS 2010)
    Place of PublicationUtrecht
    Number of pages6
    ISBN (Print)978-90-73461-67-3
    Publication statusPublished - 18 Nov 2010
    EventWorkshop on PROGram for Research on Embedded Systems and Software, PROGRESS 2010 - Veldhoven, Netherlands
    Duration: 18 Nov 201019 Nov 2010

    Publication series

    PublisherSTW Technology Foundation


    WorkshopWorkshop on PROGram for Research on Embedded Systems and Software, PROGRESS 2010
    Abbreviated titlePROGRESS


    • METIS-277454
    • IR-75095
    • EWI-18902

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