As embedded systems are becoming increasingly complex, the design process and verification have become very time-consuming. Additionally, specifying hardware manually in a low-level hardware description language like VHDL is usually an error-prone task. In our group, a tool (the ClaSH compiler) was developed to generate fully synthesisable VHDL code from a specification given in the functional programming language Haskell. In this paper, we present a comparison between two implementations of the same design by using ClaSH and hand-written VHDL. The design is a simple dataflow processor. As measures of interest area, performance, power consumption and source lines of code (SLOC) are used.
The obtained results indicate that the ClaSH -generated VHDL code as well as the netlist after synthesis and place and route are functionally correct. The placed and routed hand-written VHDL code has also the correct behaviour. Furthermore, a similar performance is achieved. The power consumption is even lower for the ClaSH implementation. The SLOC for ClaSH is considerably smaller and it is possible to specify the design in a much higher level of abstraction compared to VHDL.
|Title of host publication||Proceedings of the Workshop on PROGram for Research on Embedded Systems and Software (PROGRESS 2010)|
|Place of Publication||Utrecht|
|Number of pages||6|
|Publication status||Published - 18 Nov 2010|
|Event||Workshop on PROGram for Research on Embedded Systems and Software, PROGRESS 2010 - Veldhoven, Netherlands|
Duration: 18 Nov 2010 → 19 Nov 2010
|Publisher||STW Technology Foundation|
|Workshop||Workshop on PROGram for Research on Embedded Systems and Software, PROGRESS 2010|
|Period||18/11/10 → 19/11/10|