Comparing DLLs and Shift Registers for Low-Jitter Multi-phase Clock Generation

In this paper we compare a Shift Register (SR) to a Delay Locked Loop (DLL) for Multi Phase Clock Generation (MPCG), and motivate why a SR is often better. For a given power budget, we show that a SR generates less jitter than a DLL when both are realized with Current Mode Logic (CML) circuits and white noise is assumed. This is due to differences in jitter accumulation and the possibility to choose latch delays in a SR much smaller than the delays of DLL elements. For N-phase clock generation, the SR also functions as a divide-by-N and requires a VCO with N times higher frequency than the DLL counterpart. However, this can be done in a power neutral way and can even have advantages like higher quality factor and less area for the inductors.