Comparison of electrical techniques for temperature evaluation in power MOS transistors

A. Ferrara; P.G. Steeneken; K. Reimann; A. Heringa; L. Yan; B.K. Boksteen; M. Swanenberg; G.E.J. Koops; A.J. Scholten; R. Surdeanu; Jurriaan Schmitz; Raymond Josephus Engelbart Hueting

doi:10.1109/ICMTS.2013.6528156

Comparison of electrical techniques for temperature evaluation in power MOS transistors

A. Ferrara, P.G. Steeneken, K. Reimann, A. Heringa, L. Yan, B.K. Boksteen, M. Swanenberg, G.E.J. Koops, A.J. Scholten, R. Surdeanu, Jurriaan Schmitz, Raymond Josephus Engelbart Hueting

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

Abstract

Three electrical techniques (pulsed-gate, ACconductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-oninsulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. Onwafer measurements have been performed on a thermal chuck in the temperature range 25 − 200◦C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.

Original language	English
Title of host publication	IEEE International Conference on Microelectronic Test Structures (ICMTS 2013)
Place of Publication	USA
Publisher	IEEE
Pages	115-120
Number of pages	6
ISBN (Print)	978-1-4673-4848-5
DOIs	https://doi.org/10.1109/ICMTS.2013.6528156
Publication status	Published - 26 Mar 2013
Event	26th IEEE International Conference on Microelectronic Test Structures, ICMTS 2013 - Osaka, Japan Duration: 25 Mar 2013 → 28 Mar 2013 Conference number: 26 http://www.homepages.ed.ac.uk/ajw/ICMTS/prog13.html

Publication series

Name
Publisher	IEEE
ISSN (Print)	1071-9032

Conference

Conference	26th IEEE International Conference on Microelectronic Test Structures, ICMTS 2013
Abbreviated title	ICMTS
Country	Japan
City	Osaka
Period	25/03/13 → 28/03/13
Internet address	http://www.homepages.ed.ac.uk/ajw/ICMTS/prog13.html

Keywords

EWI-24307
AC-conductance
thermal resistance
sense-diode
METIS-302642
METIS-297985
pulsed-gate
Temperature
self-heating
IR-87590
power MOS

Access to Document

10.1109/ICMTS.2013.6528156

http://eprints.eemcs.utwente.nl/secure2/24307/01/ferrara_icmts.pdf

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Ferrara, A., Steeneken, P. G., Reimann, K., Heringa, A., Yan, L., Boksteen, B. K., Swanenberg, M., Koops, G. E. J., Scholten, A. J., Surdeanu, R., Schmitz, J., & Hueting, R. J. E. (2013). Comparison of electrical techniques for temperature evaluation in power MOS transistors. In IEEE International Conference on Microelectronic Test Structures (ICMTS 2013) (pp. 115-120). IEEE. https://doi.org/10.1109/ICMTS.2013.6528156

Ferrara, A. ; Steeneken, P.G. ; Reimann, K. ; Heringa, A. ; Yan, L. ; Boksteen, B.K. ; Swanenberg, M. ; Koops, G.E.J. ; Scholten, A.J. ; Surdeanu, R. ; Schmitz, Jurriaan ; Hueting, Raymond Josephus Engelbart. / Comparison of electrical techniques for temperature evaluation in power MOS transistors. IEEE International Conference on Microelectronic Test Structures (ICMTS 2013). USA : IEEE, 2013. pp. 115-120

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title = "Comparison of electrical techniques for temperature evaluation in power MOS transistors",

abstract = "Three electrical techniques (pulsed-gate, ACconductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-oninsulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. Onwafer measurements have been performed on a thermal chuck in the temperature range 25 − 200◦C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.",

keywords = "EWI-24307, AC-conductance, thermal resistance, sense-diode, METIS-302642, METIS-297985, pulsed-gate, Temperature, self-heating, IR-87590, power MOS",

author = "A. Ferrara and P.G. Steeneken and K. Reimann and A. Heringa and L. Yan and B.K. Boksteen and M. Swanenberg and G.E.J. Koops and A.J. Scholten and R. Surdeanu and Jurriaan Schmitz and Hueting, {Raymond Josephus Engelbart}",

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booktitle = "IEEE International Conference on Microelectronic Test Structures (ICMTS 2013)",

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note = "26th IEEE International Conference on Microelectronic Test Structures, ICMTS 2013, ICMTS ; Conference date: 25-03-2013 Through 28-03-2013",

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Ferrara, A, Steeneken, PG, Reimann, K, Heringa, A, Yan, L, Boksteen, BK, Swanenberg, M, Koops, GEJ, Scholten, AJ, Surdeanu, R, Schmitz, J & Hueting, RJE 2013, Comparison of electrical techniques for temperature evaluation in power MOS transistors. in IEEE International Conference on Microelectronic Test Structures (ICMTS 2013). IEEE, USA, pp. 115-120, 26th IEEE International Conference on Microelectronic Test Structures, ICMTS 2013, Osaka, Japan, 25/03/13. https://doi.org/10.1109/ICMTS.2013.6528156

Comparison of electrical techniques for temperature evaluation in power MOS transistors. / Ferrara, A.; Steeneken, P.G.; Reimann, K.; Heringa, A.; Yan, L.; Boksteen, B.K.; Swanenberg, M.; Koops, G.E.J.; Scholten, A.J.; Surdeanu, R.; Schmitz, Jurriaan ; Hueting, Raymond Josephus Engelbart.

IEEE International Conference on Microelectronic Test Structures (ICMTS 2013). USA : IEEE, 2013. p. 115-120.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Comparison of electrical techniques for temperature evaluation in power MOS transistors

AU - Ferrara, A.

AU - Steeneken, P.G.

AU - Reimann, K.

AU - Heringa, A.

AU - Yan, L.

AU - Boksteen, B.K.

AU - Swanenberg, M.

AU - Koops, G.E.J.

AU - Scholten, A.J.

AU - Surdeanu, R.

AU - Schmitz, Jurriaan

AU - Hueting, Raymond Josephus Engelbart

N1 - Conference code: 26

PY - 2013/3/26

Y1 - 2013/3/26

N2 - Three electrical techniques (pulsed-gate, ACconductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-oninsulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. Onwafer measurements have been performed on a thermal chuck in the temperature range 25 − 200◦C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.

AB - Three electrical techniques (pulsed-gate, ACconductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-oninsulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. Onwafer measurements have been performed on a thermal chuck in the temperature range 25 − 200◦C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.

KW - EWI-24307

KW - AC-conductance

KW - thermal resistance

KW - sense-diode

KW - METIS-302642

KW - METIS-297985

KW - pulsed-gate

KW - Temperature

KW - self-heating

KW - IR-87590

KW - power MOS

U2 - 10.1109/ICMTS.2013.6528156

DO - 10.1109/ICMTS.2013.6528156

M3 - Conference contribution

SN - 978-1-4673-4848-5

SP - 115

EP - 120

BT - IEEE International Conference on Microelectronic Test Structures (ICMTS 2013)

PB - IEEE

CY - USA

T2 - 26th IEEE International Conference on Microelectronic Test Structures, ICMTS 2013

Y2 - 25 March 2013 through 28 March 2013

ER -