Comparison of gate capacitance extraction methodologies

S.N.R. Kazmi, Jurriaan Schmitz

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    Abstract

    In recent years, many new capacitance-voltage measurement approaches have been presented in literature. New approaches became necessary with the rapidly increasing gate current density in newer CMOS generations. Here we present a simulation platform using Silvaco software, to describe the full chain from fabrication process until signal interpretation of an NMOS C-V test structure. The platform allows a verification of the validity of an assumed extraction procedure from high-frequency or RF C-V measurements.
    Original languageUndefined
    Title of host publicationProceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008)
    Place of PublicationUtrecht, The Netherlands
    PublisherSTW
    Pages562-564
    Number of pages3
    ISBN (Print)978-90-73461-56-7
    Publication statusPublished - 27 Nov 2008
    Event11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008 - Veldhoven, Netherlands
    Duration: 27 Nov 200828 Nov 2008
    Conference number: 11

    Publication series

    Name
    PublisherTechnology Foundation STW
    NumberWoTUG-31

    Workshop

    Workshop11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008
    Abbreviated titleSAFE
    CountryNetherlands
    CityVeldhoven
    Period27/11/0828/11/08

    Keywords

    • SC-CICC: Characterization of IC Components
    • METIS-254998
    • IR-62607
    • EWI-14607

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