Comparison of gate capacitance extraction methodologies

S.N.R. Kazmi; Jurriaan Schmitz

Comparison of gate capacitance extraction methodologies

S.N.R. Kazmi
, Jurriaan Schmitz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Downloads (Pure)

Abstract

In recent years, many new capacitance-voltage measurement approaches have been presented in literature. New approaches became necessary with the rapidly increasing gate current density in newer CMOS generations. Here we present a simulation platform using Silvaco software, to describe the full chain from fabrication process until signal interpretation of an NMOS C-V test structure. The platform allows a verification of the validity of an assumed extraction procedure from high-frequency or RF C-V measurements.

Original language	Undefined
Title of host publication	Proceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008)
Place of Publication	Utrecht, The Netherlands
Publisher	STW
Pages	562-564
Number of pages	3
ISBN (Print)	978-90-73461-56-7
Publication status	Published - 27 Nov 2008
Event	11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008 - Veldhoven, Netherlands Duration: 27 Nov 2008 → 28 Nov 2008 Conference number: 11

Publication series

Name
Publisher	Technology Foundation STW
Number	WoTUG-31

Workshop

Workshop	11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008
Abbreviated title	SAFE
Country/Territory	Netherlands
City	Veldhoven
Period	27/11/08 → 28/11/08

Keywords

SC-CICC: Characterization of IC Components
METIS-254998
IR-62607
EWI-14607

Access to Document

http://eprints.eemcs.utwente.nl/secure2/14607/01/kazmi.pdf

Cite this

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title = "Comparison of gate capacitance extraction methodologies",

abstract = "In recent years, many new capacitance-voltage measurement approaches have been presented in literature. New approaches became necessary with the rapidly increasing gate current density in newer CMOS generations. Here we present a simulation platform using Silvaco software, to describe the full chain from fabrication process until signal interpretation of an NMOS C-V test structure. The platform allows a verification of the validity of an assumed extraction procedure from high-frequency or RF C-V measurements.",

keywords = "SC-CICC: Characterization of IC Components, METIS-254998, IR-62607, EWI-14607",

author = "S.N.R. Kazmi and Jurriaan Schmitz",

year = "2008",

month = nov,

day = "27",

language = "Undefined",

isbn = "978-90-73461-56-7",

publisher = "STW",

number = "WoTUG-31",

pages = "562--564",

booktitle = "Proceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008)",

note = "11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008 ; Conference date: 27-11-2008 Through 28-11-2008",

}

Kazmi, SNR & Schmitz, J 2008, Comparison of gate capacitance extraction methodologies. in Proceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008). STW, Utrecht, The Netherlands, pp. 562-564, 11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008, Veldhoven, Netherlands, 27/11/08. <http://eprints.eemcs.utwente.nl/secure2/14607/01/kazmi.pdf>

Comparison of gate capacitance extraction methodologies. / Kazmi, S.N.R.; Schmitz, Jurriaan.
Proceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008). Utrecht, The Netherlands: STW, 2008. p. 562-564.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Comparison of gate capacitance extraction methodologies

AU - Kazmi, S.N.R.

AU - Schmitz, Jurriaan

N1 - Conference code: 11

PY - 2008/11/27

Y1 - 2008/11/27

N2 - In recent years, many new capacitance-voltage measurement approaches have been presented in literature. New approaches became necessary with the rapidly increasing gate current density in newer CMOS generations. Here we present a simulation platform using Silvaco software, to describe the full chain from fabrication process until signal interpretation of an NMOS C-V test structure. The platform allows a verification of the validity of an assumed extraction procedure from high-frequency or RF C-V measurements.

AB - In recent years, many new capacitance-voltage measurement approaches have been presented in literature. New approaches became necessary with the rapidly increasing gate current density in newer CMOS generations. Here we present a simulation platform using Silvaco software, to describe the full chain from fabrication process until signal interpretation of an NMOS C-V test structure. The platform allows a verification of the validity of an assumed extraction procedure from high-frequency or RF C-V measurements.

KW - SC-CICC: Characterization of IC Components

KW - METIS-254998

KW - IR-62607

KW - EWI-14607

M3 - Conference contribution

SN - 978-90-73461-56-7

SP - 562

EP - 564

BT - Proceedings of the 11th annual workshop on semiconductor advances for future electronics and sensors (SAFE 2008)

PB - STW

CY - Utrecht, The Netherlands

T2 - 11th Annual Workshop on Semiconductor Advances for Future Electronics and Sensors, SAFE 2008

Y2 - 27 November 2008 through 28 November 2008

ER -