TY - JOUR
T1 - Complementary resistive switch-based arithmetic logic implementations using material implication
AU - Yang, Yuanfan
AU - Mathew, J.
AU - Pontarelli, S.
AU - Ottavi, M.
AU - Pradhan, D.K.
PY - 2016
Y1 - 2016
N2 - Memristors are considered among the most promising future building blocks of next-generation digital systems. This paper focuses on specific ways to implement logic and arithmetic unit using memristors. In particular, we present a set of complementary resistive switching (CRS)-based stateful logic operations that use material implication to provide the basic logic functionalities needed to realize logic circuits. The proposed solution benefits from the exponential reduction in sneak path current in crossbar implemented logic. This paper also presents a closed-form expression for sneak current and analyzes the impact of device variation on the behavior of the proposed logic blocks. Our technique, as other similar techniques proposed in the literature, requires several sequential steps to perform the computation. However, in this paper, we show that only three steps are required for implementing N input nand gate, whereas previously proposed memristor-based stateful logic needs N + 1 steps. We validated the effectiveness of our solution through cadence spectre circuit simulator on a number of logic circuits. Finally, we extended this approach for arithmetic circuits with an 8-bit adder and a 4-bit multiplier.
AB - Memristors are considered among the most promising future building blocks of next-generation digital systems. This paper focuses on specific ways to implement logic and arithmetic unit using memristors. In particular, we present a set of complementary resistive switching (CRS)-based stateful logic operations that use material implication to provide the basic logic functionalities needed to realize logic circuits. The proposed solution benefits from the exponential reduction in sneak path current in crossbar implemented logic. This paper also presents a closed-form expression for sneak current and analyzes the impact of device variation on the behavior of the proposed logic blocks. Our technique, as other similar techniques proposed in the literature, requires several sequential steps to perform the computation. However, in this paper, we show that only three steps are required for implementing N input nand gate, whereas previously proposed memristor-based stateful logic needs N + 1 steps. We validated the effectiveness of our solution through cadence spectre circuit simulator on a number of logic circuits. Finally, we extended this approach for arithmetic circuits with an 8-bit adder and a 4-bit multiplier.
UR - http://www.scopus.com/inward/record.url?eid=2-s2.0-84963900776&partnerID=MN8TOARS
U2 - 10.1109/TNANO.2015.2504841
DO - 10.1109/TNANO.2015.2504841
M3 - Article
SN - 1536-125X
VL - 15
SP - 94
EP - 108
JO - IEEE transactions on nanotechnology
JF - IEEE transactions on nanotechnology
IS - 1
ER -