In this article we present the results of partitioning the OFDM baseband processing of a DRM receiver into smaller independent processes. Furthermore, we give a short introduction into the relevant parts of the DRM standard. Based on the number of multiplications and additions we can map individual processes on a heterogeneous multitile architecture. This architecture can meet both the computational demands as well as the restricted energy budget.
|Title of host publication||15th Annual Workshop on Circuits Systems and Signal Processing (ProRISC)|
|Place of Publication||Utrecht|
|Publication status||Published - Nov 2004|
|Event||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004 - Veldhoven, Netherlands|
Duration: 25 Nov 2004 → 26 Nov 2004
Conference number: 15
|Publisher||Technology Foundation, STW|
|Conference||15th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2004|
|Period||25/11/04 → 26/11/04|
- EC Grant Agreement nr.: FP6/001908
- CAES-EEA: Efficient Embedded Architectures
Wolkotte, P. T., Smit, G. J. M., & Smit, L. T. (2004). Complexity analysis for mapping a DRM receiver on a heterogeneous tiled architecture. In 15th Annual Workshop on Circuits Systems and Signal Processing (ProRISC) (pp. 442-446). Utrecht: STW.