Computer-Aided Test Flow in Core-Based Design

V. Zivkovic; R.J.W.T. Tangelder; H.G. Kerkhoff

doi:10.1109/ICMEL.2000.838790

Computer-Aided Test Flow in Core-Based Design

V. Zivkovic, R.J.W.T. Tangelder, H.G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

196 Downloads (Pure)

Abstract

This paper copes with the test-pattern generation and fault coverage determination in the core based design. The basic core-test strategy that one has to apply in the core-based design is stated in this work. A Computer-Aided Test (CAT) flow is proposed resulting in accurate fault coverage of embedded cores. The CAT now is applied to a few cores within the Philips Core Test Pilot IC project

Original language	English
Title of host publication	22nd International Conference on Microelectronics
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	715-718
Number of pages	4
Volume	2
ISBN (Print)	0-7803-5235-1
DOIs	https://doi.org/10.1109/ICMEL.2000.838790
Publication status	Published - 14 May 2000
Event	22nd International Conference on Microelectronics, 2000 - Nis, Yugoslavia Duration: 14 May 2000 → 17 May 2000

Conference

Conference	22nd International Conference on Microelectronics, 2000
Period	14/05/00 → 17/05/00
Other	14-17 May 2000

Keywords

n/a OA procedure

Access to Document

10.1109/ICMEL.2000.838790

3 Citations
1 Article

Computer-Aided Test Flow in Core-Based Design
Zivkovic, V., Tangelder, R. J. W. T. & Kerkhoff, H. G., 2000, In: Microelectronics journal. 31, 11/12, p. 999-1008
Research output: Contribution to journal › Article › Academic › peer-review
3 Downloads (Pure)

Cite this

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abstract = "This paper copes with the test-pattern generation and fault coverage determination in the core based design. The basic core-test strategy that one has to apply in the core-based design is stated in this work. A Computer-Aided Test (CAT) flow is proposed resulting in accurate fault coverage of embedded cores. The CAT now is applied to a few cores within the Philips Core Test Pilot IC project",

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AB - This paper copes with the test-pattern generation and fault coverage determination in the core based design. The basic core-test strategy that one has to apply in the core-based design is stated in this work. A Computer-Aided Test (CAT) flow is proposed resulting in accurate fault coverage of embedded cores. The CAT now is applied to a few cores within the Philips Core Test Pilot IC project

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Computer-Aided Test Flow in Core-Based Design

Abstract

Conference

Keywords

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Research output

Computer-Aided Test Flow in Core-Based Design

Cite this