Computer-Aided Test Flow in Core-Based Design

This paper copes with the efficient test-pattern generation in a core-based design. A consistent Computer-Aided Test (CAT) flow is proposed based on the required core-test strategy. It generates a test-pattern set for the embedded cores with high fault coverage and low DfT area overhead. The CAT flow is applied within Philips Core Test Pilot IC project. In addition, it will be shown how the proposed CAT flow can be further modified and used to decrease the number of test patterns within a VLIW TTA processor core. Besides reducing the number of test cycles, it also maintains a high fault coverage and keeps the DfT area low.