Computer-Aided Test Flow in Core-Based Design

V. Zivkovic; R.J.W.T. Tangelder; H.G. Kerkhoff

doi:10.1016/S0026-2692(00)00089-6

Computer-Aided Test Flow in Core-Based Design

V. Zivkovic, R.J.W.T. Tangelder, H.G. Kerkhoff

Research output: Contribution to journal › Article › Academic › peer-review

3 Downloads (Pure)

Abstract

This paper copes with the efficient test-pattern generation in a core-based design. A consistent Computer-Aided Test (CAT) flow is proposed based on the required core-test strategy. It generates a test-pattern set for the embedded cores with high fault coverage and low DfT area overhead. The CAT flow is applied within Philips Core Test Pilot IC project. In addition, it will be shown how the proposed CAT flow can be further modified and used to decrease the number of test patterns within a VLIW TTA processor core. Besides reducing the number of test cycles, it also maintains a high fault coverage and keeps the DfT area low.

Original language	English
Pages (from-to)	999-1008
Journal	Microelectronics journal
Volume	31
Issue number	11/12
DOIs	https://doi.org/10.1016/S0026-2692(00)00089-6
Publication status	Published - 2000

Keywords

Test pattern generation
Test synthesis
VLIW test
Embedded core test
n/a OA procedure

Access to Document

10.1016/S0026-2692(00)00089-6

1 Conference contribution

Computer-Aided Test Flow in Core-Based Design
Zivkovic, V., Tangelder, R. J. W. T. & Kerkhoff, H. G., 14 May 2000, 22nd International Conference on Microelectronics. Piscataway, NJ: IEEE, Vol. 2. p. 715-718 4 p.
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
3 Citations (Scopus)

196 Downloads (Pure)

Cite this

@article{4f3c719b01f94f2fbcef366730ace5df,

title = "Computer-Aided Test Flow in Core-Based Design",

abstract = "This paper copes with the efficient test-pattern generation in a core-based design. A consistent Computer-Aided Test (CAT) flow is proposed based on the required core-test strategy. It generates a test-pattern set for the embedded cores with high fault coverage and low DfT area overhead. The CAT flow is applied within Philips Core Test Pilot IC project. In addition, it will be shown how the proposed CAT flow can be further modified and used to decrease the number of test patterns within a VLIW TTA processor core. Besides reducing the number of test cycles, it also maintains a high fault coverage and keeps the DfT area low.",

keywords = "Test pattern generation, Test synthesis, VLIW test, Embedded core test, n/a OA procedure",

author = "V. Zivkovic and R.J.W.T. Tangelder and H.G. Kerkhoff",

year = "2000",

doi = "10.1016/S0026-2692(00)00089-6",

language = "English",

volume = "31",

pages = "999--1008",

journal = "Microelectronics journal",

issn = "0026-2692",

publisher = "Elsevier Ltd",

number = "11/12",

}

TY - JOUR

T1 - Computer-Aided Test Flow in Core-Based Design

AU - Zivkovic, V.

AU - Tangelder, R.J.W.T.

AU - Kerkhoff, H.G.

PY - 2000

Y1 - 2000

N2 - This paper copes with the efficient test-pattern generation in a core-based design. A consistent Computer-Aided Test (CAT) flow is proposed based on the required core-test strategy. It generates a test-pattern set for the embedded cores with high fault coverage and low DfT area overhead. The CAT flow is applied within Philips Core Test Pilot IC project. In addition, it will be shown how the proposed CAT flow can be further modified and used to decrease the number of test patterns within a VLIW TTA processor core. Besides reducing the number of test cycles, it also maintains a high fault coverage and keeps the DfT area low.

AB - This paper copes with the efficient test-pattern generation in a core-based design. A consistent Computer-Aided Test (CAT) flow is proposed based on the required core-test strategy. It generates a test-pattern set for the embedded cores with high fault coverage and low DfT area overhead. The CAT flow is applied within Philips Core Test Pilot IC project. In addition, it will be shown how the proposed CAT flow can be further modified and used to decrease the number of test patterns within a VLIW TTA processor core. Besides reducing the number of test cycles, it also maintains a high fault coverage and keeps the DfT area low.

KW - Test pattern generation

KW - Test synthesis

KW - VLIW test

KW - Embedded core test

KW - n/a OA procedure

U2 - 10.1016/S0026-2692(00)00089-6

DO - 10.1016/S0026-2692(00)00089-6

M3 - Article

SN - 0026-2692

VL - 31

SP - 999

EP - 1008

JO - Microelectronics journal

JF - Microelectronics journal

IS - 11/12

ER -

Computer-Aided Test Flow in Core-Based Design

Abstract

Keywords

Access to Document

Fingerprint

Research output

Computer-Aided Test Flow in Core-Based Design

Cite this