Crystallographic Silicon-etching for ultra-high aspect-ratio FinFET

V. Jovanović*, T. Suligoj, L. K. Nanver

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

The fabrication process for the FinFET with ultra-high fin-height to fin-width aspect-ratio is presented. The processing is based on the crystallographic etching of (110) bulk silicon-wafers by TMAH to expose the vertical (111) planes. The nitride-spacers are used as the hard-mask for the fin-etching and the fins are isolated by the planarization and etch-back of the thick isolation oxide. The demonstration devices exhibit nearly ideal S of 62-64 mV/dec and DIBL of 10 mV/V or lower, for the gate-length of 410 nm and the height of the active part of the fin of 400 nm. The output current is limited by the large series resistances for both pFETs and nFETs, and additionally by the gate-depletion in nFETs, but large currents per fin, above 30 μA for pFET are achieved due to tall fin-structure.

Original languageEnglish
Title of host publicationECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages313-320
Number of pages8
Volume13
Edition1
DOIs
Publication statusPublished - 13 Nov 2008
Externally publishedYes
Event213th ECS Meeting 2008 - Phoenix, AZ, United States
Duration: 18 May 200822 May 2008
https://www.electrochem.org/213

Conference

Conference213th ECS Meeting 2008
CountryUnited States
CityPhoenix, AZ
Period18/05/0822/05/08
Internet address

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Cite this

Jovanović, V., Suligoj, T., & Nanver, L. K. (2008). Crystallographic Silicon-etching for ultra-high aspect-ratio FinFET. In ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment (1 ed., Vol. 13, pp. 313-320) https://doi.org/10.1149/1.2911512