This paper focuses on the long-term electrical degradation of hydrogenated amorphous silicon (a- Si:H)/silicon nitride (SiN) thin-film transistors (TFTs). Different from the classical method where the electrical degradation of a-Si:H/SiN TFTs is quantified by the shift of the threshold voltage after a period of stress, the authors choose to describe the degradation in terms of drain–current transients that appear during alternative periods of electrical stress. It is shown that the contributions of charge trapping and defect creation to the drain–current degradation can be discriminated based on stress time, stress voltage, and temperature. A numerical model with variable parameters is proposed to fit both short- and long-term transients. This paper shows that the long-term current degradation is related to the changes in the interface trapped charge, whereas the creation of the defects dominates the short-term current degradation.
- SC-ICRY: Integrated Circuit Reliability and Yield