Current source array

Andreia Cathelin (Inventor), Bram Nauta (Inventor)

Research output: PatentProfessional

20 Downloads (Pure)

Abstract

A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.
Original languageUndefined
Patent numberUS9455689B2
Priority date19/11/14
Publication statusPublished - 27 Sep 2016

Keywords

  • METIS-305903
  • IR-101863
  • EWI-24796

Cite this

Cathelin, A., & Nauta, B. (2016). Current source array. (Patent No. US9455689B2).
Cathelin, Andreia (Inventor) ; Nauta, Bram (Inventor). / Current source array. Patent No.: US9455689B2.
@misc{98c156d79fd0475cbeabc1c4c25b50c7,
title = "Current source array",
abstract = "A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.",
keywords = "METIS-305903, IR-101863, EWI-24796",
author = "Andreia Cathelin and Bram Nauta",
note = "https://patents.google.com/patent/US20150137874A1/en?inventor=Bram+Nauta&after=20140101; US9455689B2",
year = "2016",
month = "9",
day = "27",
language = "Undefined",
type = "Patent",

}

Cathelin, A & Nauta, B 2016, Current source array, Patent No. US9455689B2.

Current source array. / Cathelin, Andreia (Inventor); Nauta, Bram (Inventor).

Patent No.: US9455689B2.

Research output: PatentProfessional

TY - PAT

T1 - Current source array

AU - Cathelin, Andreia

AU - Nauta, Bram

N1 - https://patents.google.com/patent/US20150137874A1/en?inventor=Bram+Nauta&after=20140101

PY - 2016/9/27

Y1 - 2016/9/27

N2 - A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

AB - A Silicon On Insulator current source array includes input control for receiving a control voltage, a first reference input for receiving a first reference voltage, and a second reference input for receiving a second reference voltage. A chain of several Silicon On Insulator MOS transistors, of the same type, have control electrodes all connected to the input control, first conduction electrodes are all connected to the first reference input, and second conduction electrodes are respectively connected to the second reference input through several load circuits respectively configured to be traversed by several currents when the several transistors are ON upon application of the control voltage on the input control. An input bias is coupled to a semiconductor well located below an insulating buried layer located below the chain of transistors for receiving a biasing voltage difference.

KW - METIS-305903

KW - IR-101863

KW - EWI-24796

M3 - Patent

M1 - US9455689B2

ER -

Cathelin A, Nauta B, inventors. Current source array. US9455689B2. 2016 Sep 27.