In this paper, a two-step methodology is introduced to analyse the mapping of Cyclostationary Feature Detection (CFD) onto a multi-core processing platform. In the first step, the tasks to be executed by each core are determined in a structured way using techniques known form the design of array processors. In the second step, the implementation of tasks on a processing core is analysed. Using this methodology, it is shown that calculating a 127 x 127 Discrete Spectral Correlation Function requires approximately 140 microseconds on a tiled System on Chip (SoC) with 4 Montium cores.
|Publisher||European Design and Automation Association|
|Conference||2007 Design, Automation & Test in Europe Conference & Exhibition, DATE 2007|
|Period||16/04/07 → 20/04/07|
- Reconfigurable processing
- System on Chip
- Cognitive Radio
- Spectrum Sensing