Cyclostationary Feature Detection on a tiled-SoC

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    Abstract

    In this paper, a two-step methodology is introduced to analyse the mapping of Cyclostationary Feature Detection (CFD) onto a multi-core processing platform. In the first step, the tasks to be executed by each core are determined in a structured way using techniques known form the design of array processors. In the second step, the implementation of tasks on a processing core is analysed. Using this methodology, it is shown that calculating a 127 x 127 Discrete Spectral Correlation Function requires approximately 140 microseconds on a tiled System on Chip (SoC) with 4 Montium cores.
    Original languageUndefined
    Title of host publicationDATE2007 Proceedings
    PublisherEuropean Design and Automation Association
    Pages171-176
    Number of pages6
    ISBN (Print)978-3-9810801-2-4
    DOIs
    Publication statusPublished - Apr 2007
    Event2007 Design, Automation & Test in Europe Conference & Exhibition, DATE 2007 - Nice, France
    Duration: 16 Apr 200720 Apr 2007

    Publication series

    Name
    PublisherEuropean Design and Automation Association
    Number07TH8938

    Conference

    Conference2007 Design, Automation & Test in Europe Conference & Exhibition, DATE 2007
    Abbreviated titleDATE
    CountryFrance
    CityNice
    Period16/04/0720/04/07

    Keywords

    • EWI-9853
    • METIS-242169
    • Reconfigurable processing
    • IR-67112
    • System on Chip
    • Cognitive Radio
    • Spectrum Sensing

    Cite this

    Kokkeler, A. B. J., Smit, G. J. M., Krol, T., & Kuper, J. (2007). Cyclostationary Feature Detection on a tiled-SoC. In DATE2007 Proceedings (pp. 171-176). [10.1109/DATE.2007.364586] European Design and Automation Association. https://doi.org/10.1109/DATE.2007.364586