DARS: An EDA framework for reliability and functional safety management of system-on-chips

Electronic design automation tools used for Design-For-Test infrastructure insertion have often relied on test standards (e.g. IEEE 1149.1, 1500 and 1687) as a structured methodology for IC test access, which consequently reduce the design cost for DFT. The IEEE 1687 standard introduces an efficient methodology for the off-chip access of the increasing number of embedded instruments that are used for test, debug and other purposes. A subset of these instruments is also used for Reliability and functional Safety (RaS) management, while accessing them via an on-chip manager. In this paper, we present a design automation framework for the RaS management of System-on-Chips using embedded instruments, by utilizing the IEEE 1687 standard as the key enabler of this automation. The framework enables the on-chip execution of cross-layer RaS procedures by the automatic generation of a dedicated design layer for the procedures execution. The framework utilizes the IEEE 1687-defined PDL language and the pattern retargeting process for enabling a programming model for developing the RaS procedures with no regard to the instruments access procedures and their physical locations, which consequently reduce the development time of RaS procedures and enable their scalability and reusability, and hence their automation.